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1. 发明申请

WO2011012054A1 METHOD AND DEVICE FOR ELIMINATING BACKGROUND NOISE 审中-公开
标题翻译：消除背景噪声的方法和装置
公开(公告)号：WO2011012054A1
公开(公告)日：2011-02-03
申请号：PCT/CN2010/075255
申请日：2010-07-19
申请人： BYD COMPANY LIMITED , LI, Hai , XU, Kunping , YANG, Yun , FENG, Wei
发明人： LI, Hai , XU, Kunping , YANG, Yun , FENG, Wei
IPC分类号： G10L21/02
CPC分类号： G10L21/0208
摘要： A method for eliminating background noise may comprise a) detecting a characteristic value of an audio signal to obtain a characteristic signal reflecting a change trend of the audio signal; b) multiplying the characteristic signal and the audio signal to obtain a product signal; and c) 5 amplifying the product signal proportionally and outputting the amplified product signal. A device for eliminating background noise is also disclosed.
摘要翻译：消除背景噪声的方法可以包括：a）检测音频信号的特征值以获得反映音频信号的变化趋势的特征信号; b）乘以特征信号和音频信号以获得乘积信号; 和c）5成比例地放大产品信号并输出放大的产品信号。还公开了用于消除背景噪声的装置。

2. 发明申请

WO2010124561A1 MICROPHONE 审中-公开
标题翻译：麦克风
公开(公告)号：WO2010124561A1
公开(公告)日：2010-11-04
申请号：PCT/CN2010/071861
申请日：2010-04-17
申请人： BYD COMPANY LIMITED , ZHAO, Jing , YANG, Gangjian , XU, Kunping , LI, Hai , YANG, Yun , FENG, Wei
发明人： ZHAO, Jing , YANG, Gangjian , XU, Kunping , LI, Hai , YANG, Yun , FENG, Wei
IPC分类号： H04R1/00
CPC分类号： H04R19/005 , H04R19/016 , H04R2410/03
摘要： The present invention discloses a microphone, which may comprise an inner unit comprising a microphone module; a driver module coupled to the microphone module; a noise cancellation module coupled to the driver module; and a housing for accommodating the inner unit. At least two modules selected from the microphone module, the driver module and the noise cancellation module may be integrated in a chip. The microphone according to the present invention has a smaller volume with reduced technical complexity.
摘要翻译：本发明公开了一种麦克风，其可以包括包括麦克风模块的内部单元; 耦合到所述麦克风模块的驱动器模块; 耦合到所述驱动器模块的噪声消除模块; 以及用于容纳内部单元的壳体。从麦克风模块，驱动器模块和噪声消除模块中选择的至少两个模块可以集成在芯片中。根据本发明的麦克风具有较小的体积，降低了技术复杂性。

3. 发明申请

WO2010115359A1 METHOD AND DEVICE FOR ELIMINATING BACKGROUND NOISE 审中-公开
标题翻译：消除背景噪声的方法和装置
公开(公告)号：WO2010115359A1
公开(公告)日：2010-10-14
申请号：PCT/CN2010/071334
申请日：2010-03-25
申请人： BYD COMPANY LIMITED , LI, Hai , XU, Kunping , ZHANG, Lizhen , YANG, Yun , FENG, Wei
发明人： LI, Hai , XU, Kunping , ZHANG, Lizhen , YANG, Yun , FENG, Wei
IPC分类号： G10L21/02 , G10L11/02
CPC分类号： G10L21/0208 , G10L2021/02168
摘要： A method for eliminating background noise and a device thereof are provided. The method may comprise the steps of : detecting an effective value of a received audio signal to generate an output signal corresponding to an average power of the received audio signal (step A); generating a noise eliminating control signal by comparing the output signal corresponding to the average power signal with first threshold determined based on the difference between an average power of the voice signal and an average power of the noise signal (step B); eliminating the noise signal from the received audio signal, and amplifying the voice signal in the received audio signal with the control of the noise eliminating control signal. Based on the method and device, the background noise may be eliminated effectively.
摘要翻译：提供消除背景噪声的方法及其装置。该方法可以包括以下步骤：检测所接收的音频信号的有效值以产生对应于所接收的音频信号的平均功率的输出信号（步骤A）; 通过将对应于平均功率信号的输出信号与基于语音信号的平均功率和噪声信号的平均功率之间的差异确定的第一阈值相比较来产生噪声消除控制信号（步骤B）; 消除来自接收到的音频信号的噪声信号，并且通过噪声消除控制信号的控制来放大所接收的音频信号中的语音信号。基于该方法和装置，可以有效地消除背景噪声。

4. 发明申请

WO2011005809A1 NON-VOLATILE MEMORY ARRAY WITH RESISTIVE SENSE ELEMENT BLOCK ERASE AND UNI-DIRECTIONAL WRITE 审中-公开
标题翻译：具有电阻感应元件块非易失性存储器阵列和单向写入
公开(公告)号：WO2011005809A1
公开(公告)日：2011-01-13
申请号：PCT/US2010/041134
申请日：2010-07-07
申请人： SEAGATE TECHNOLOGY LLC , REED, Daniel , LU, Young , CARTER, Andrew , LI, Hai
发明人： REED, Daniel , LU, Young , CARTER, Andrew , LI, Hai
IPC分类号： G11C11/16 , G11C13/02 , G11C16/02 , H01L43/08
CPC分类号： H01L27/228 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2013/0088 , G11C2213/79
摘要： A non-volatile memory cell (130) and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device (132) and a resistive sense element (RSE) (110) connected in series between first (138) and second (141A) control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.
摘要翻译：公开了一种非易失性存储器单元（130）和相关联的使用方法。根据各种实施例，存储单元包括串联连接在第一（138）和第二（141A）控制线之间的开关装置（132）和电阻感测元件（RSE）（110）。第一控制线被提供可变电压，第二控制线保持在固定的参考电压。 RSE的第一电阻状态通过将第一控制线的可变电压降低到第二控制线的固定参考电压以下来编程，以使体电流流过开关器件。 RSE的不同的第二电阻状态通过将第一控制线的可变电压升高到固定参考电压以上而使漏源电流流过开关器件来编程。

5. 发明申请

WO2010117654A1 PREDICTIVE PRE-HEATING OF NON-VOLATILE MEMORY CELLS 审中-公开
标题翻译：非挥发性记忆细胞的预测性预热
公开(公告)号：WO2010117654A1
公开(公告)日：2010-10-14
申请号：PCT/US2010/028628
申请日：2010-03-25
申请人： SEAGATE TECHNOLOGY LLC , CHEN, Yiran , LI, Hai , LIU, Harry Hongyue , DIMITROV, Dimitar V. , WANG, Alan Xuguang , WANG, Xiaobin
发明人： CHEN, Yiran , LI, Hai , LIU, Harry Hongyue , DIMITROV, Dimitar V. , WANG, Alan Xuguang , WANG, Xiaobin
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method (180) and apparatus (106) for using thermal preconditioning to write data to a non- volatile memory cell (120), such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non- volatile first memory cell associated with a first block address (184). Thermal preconditioning is concurrently applied to a non-volatile second memory cell (188) associated with a second block address selected in response to the first block address (186) selection such that the record block address is an address of a block which has a relatively high probability of being selected in a write operation subsequent to the write operation of the non-volatile first memory cell.
摘要翻译：一种用于使用热预处理将数据写入非易失性存储单元（120）的方法（180）和装置（106），诸如自旋转矩传递随机存取存储器（STRAM）存储单元。在一些实施例中，将逻辑状态写入与第一块地址相关联的未条件非易失性第一存储单元（184）。热预处理同时应用于与响应于第一块地址（186）选择而选择的第二块地址相关联的非易失性第二存储器单元（188），使得记录块地址是具有相对在非易失性第一存储单元的写入操作之后的写入操作中被选择的高概率。

6. 发明申请

WO2009158055A1 SPIN-TRANSFER TORQUE MEMORY NON-DESTRUCTIVE SELF-REFERENCE READ METHOD 审中-公开
标题翻译：转子转子记忆体非破坏性自参考读取方法
公开(公告)号：WO2009158055A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/038935
申请日：2009-03-31
申请人： SEAGATE TECHNOLOGY LLC , CHEN, Yiran , LI, Hai , LIU, Hongyue , WANG, Ran , DIMITROV, Dimitar
发明人： CHEN, Yiran , LI, Hai , LIU, Hongyue , WANG, Ran , DIMITROV, Dimitar
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/1693
摘要： A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
摘要翻译：描述了自旋转移力矩存储装置和非破坏性自参考读取方案。读取自旋转移力矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压并将第一位线读取电压存储在第一电压存储装置中。磁性隧道结数据单元具有第一电阻状态。然后，该方法包括通过具有第一电阻状态的磁性隧道结数据单元施加第二读取电流并形成第二位线读取电压，并将第二位线读取电压存储在第二电压存储器件中。第一个读取电流小于第二个读取电流。然后将存储的第一位线读取电压与存储的第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

7. 发明申请

WO2010107869A1 STUCK-AT DEFECT CONDITION REPAIR FOR A NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：对非易失性存储器细胞进行STUCK-AT缺陷条件修复
公开(公告)号：WO2010107869A1
公开(公告)日：2010-09-23
申请号：PCT/US2010/027593
申请日：2010-03-17
申请人： SEAGATE TECHNOLOGY LLC , WANG, Alan, Xuguang , WANG, Xiaobin , DIMITROV, Dimitar V. , LI, Hai , XI, Haiwen , LIU, Harry Hongyue
发明人： WANG, Alan, Xuguang , WANG, Xiaobin , DIMITROV, Dimitar V. , LI, Hai , XI, Haiwen , LIU, Harry Hongyue
IPC分类号： G11C11/16 , G11C29/04
CPC分类号： G11C29/50 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C11/1697
摘要： A method (210) and apparatus (180, 200) for repairing a stuck-at defect condition in a non- volatile memory cell (124), such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element (158) has a magnetic tunneling junction (MTJ) and a repair plane (168) located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
摘要翻译：一种用于修复诸如自旋转矩传递随机存取存储器（STRAM）的非易失性存储单元（124）中的卡入缺陷状况的方法（210）和装置（180,200）。在一些实施例中，电阻感测元件（158）具有位于电阻感测元件附近的磁性隧道结（MTJ）和修复平面（168）。修复平面在MTJ中注入磁场以修复卡住的缺陷状况。

8. 发明申请

WO2010101932A1 PROGRAMMABLE POWER SOURCE USING ARRAY OF RESISTIVE SENSE MEMORY CELLS 审中-公开
标题翻译：使用电阻感知记忆细胞阵列可编程电源
公开(公告)号：WO2010101932A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/025939
申请日：2010-03-02
申请人： SEAGATE TECHNOLOGY LLC , CHEN, Yiran , JIN, Insik , LI, Hai , DIMITROV, Dimitar, V. , WANG, Dexin
发明人： CHEN, Yiran , JIN, Insik , LI, Hai , DIMITROV, Dimitar, V. , WANG, Dexin
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source (100) which uses an array of resistive sense memory cells (152, 154), such as but not limited to STRAM cells (130) or RRAM cells (140), to provide a controlled power bias to a load (102), such as but not limited to a micro-oscillator (148, 150). In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input (160) which selectively programs at least selected ones of the memory cells to a selected resistance state.
摘要翻译：本发明的各种实施例一般涉及一种包括可编程电源（100）的装置，该可编程电源使用电阻式读出存储器单元（152,154）阵列，例如但不限于STRAM单元（130）或RRAM单元 140），以向负载（102）（例如但不限于微振荡器（148,150））提供受控的功率偏置。在一些实施例中，可编程电源包括串联连接的电阻式感测存储器单元的阵列。可编程电源将选择性可控的功率电平施加到与控制输入（160）相关联的负载，该控制输入选择性地将至少选定的一个存储器单元编程为所选择的电阻状态。

9. 发明申请

WO2010120634A1 THREE DIMENSIONALLY STACKED NON-VOLATILE MEMORY UNITS 审中-公开
标题翻译：三维尺寸非易失性存储单元
公开(公告)号：WO2010120634A1
公开(公告)日：2010-10-21
申请号：PCT/US2010/030466
申请日：2010-04-09
申请人： SEAGATE TECHNOLOGY LLC , WANG, Xuguang , LU, Yong , LI, Hai , LIU, Hongyue
发明人： WANG, Xuguang , LU, Yong , LI, Hai , LIU, Hongyue
IPC分类号： H01L27/24 , H01L27/22
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit (200) including a first transistor (210) spanning a first transistor region in a first layer of the memory unit; a second transistor (220) spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell (230) spanning a first memory region in a third layer of the memory unit; and a second RSM cell (250) spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元（200），包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管（210）跨越存储器单元的第二层中的第二晶体管区域的第二晶体管（220）; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元（230）以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元（250），其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中，第二层位于第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储区域不延伸超过第一晶体管区域和第二晶体管区域。

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