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1. 发明申请

WO2009158055A1 SPIN-TRANSFER TORQUE MEMORY NON-DESTRUCTIVE SELF-REFERENCE READ METHOD 审中-公开
标题翻译：转子转子记忆体非破坏性自参考读取方法
公开(公告)号：WO2009158055A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/038935
申请日：2009-03-31
申请人： SEAGATE TECHNOLOGY LLC , CHEN, Yiran , LI, Hai , LIU, Hongyue , WANG, Ran , DIMITROV, Dimitar
发明人： CHEN, Yiran , LI, Hai , LIU, Hongyue , WANG, Ran , DIMITROV, Dimitar
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/1693
摘要： A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
摘要翻译：描述了自旋转移力矩存储装置和非破坏性自参考读取方案。读取自旋转移力矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压并将第一位线读取电压存储在第一电压存储装置中。磁性隧道结数据单元具有第一电阻状态。然后，该方法包括通过具有第一电阻状态的磁性隧道结数据单元施加第二读取电流并形成第二位线读取电压，并将第二位线读取电压存储在第二电压存储器件中。第一个读取电流小于第二个读取电流。然后将存储的第一位线读取电压与存储的第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

2. 发明申请

WO2010120634A1 THREE DIMENSIONALLY STACKED NON-VOLATILE MEMORY UNITS 审中-公开
标题翻译：三维尺寸非易失性存储单元
公开(公告)号：WO2010120634A1
公开(公告)日：2010-10-21
申请号：PCT/US2010/030466
申请日：2010-04-09
申请人： SEAGATE TECHNOLOGY LLC , WANG, Xuguang , LU, Yong , LI, Hai , LIU, Hongyue
发明人： WANG, Xuguang , LU, Yong , LI, Hai , LIU, Hongyue
IPC分类号： H01L27/24 , H01L27/22
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit (200) including a first transistor (210) spanning a first transistor region in a first layer of the memory unit; a second transistor (220) spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell (230) spanning a first memory region in a third layer of the memory unit; and a second RSM cell (250) spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元（200），包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管（210）跨越存储器单元的第二层中的第二晶体管区域的第二晶体管（220）; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元（230）以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元（250），其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中，第二层位于第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储区域不延伸超过第一晶体管区域和第二晶体管区域。

3. 发明申请

WO2010138219A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 审中-公开
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：WO2010138219A1
公开(公告)日：2010-12-02
申请号：PCT/US2010/025193
申请日：2010-02-24
申请人： SEAGATE TECHNOLOGY LLC , JUNG, Chulmin , LIU, Hongyue , LEE, Brian , LU, Yong , SETIADI, Dadi
发明人： JUNG, Chulmin , LIU, Hongyue , LEE, Brian , LU, Yong , SETIADI, Dadi
IPC分类号： G11C16/26 , G11C11/00
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储器单元中，并且存储的电荷随后通过所选择的列从易失性存储单元中排出。在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中沿着与存储器阵列中的相应列耦合的行的每个DRAM单元，以及每列非易失性存储单元包括以NAND配置连接的闪存单元。

4. 发明申请

WO2010045184A1 VERTICALLY INTEGRATED MEMORY STRUCTURES 审中-公开
标题翻译：垂直集成存储器结构
公开(公告)号：WO2010045184A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/060431
申请日：2009-10-13
申请人： SEAGATE TECHNOLOGY LLC
发明人： WANG, Xuguang , CHEN, Yiran , DIMITROV, Dimitar , LIU, Hongyue
IPC分类号： H01L27/24 , H01L27/22
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
摘要： A device including a transistor (410) that includes a source region (412); a drain region (414); and a channel region (418), wherein the channel region electrically connects the source region and the drain region along a channel axis (A); and a memory cell (430), wherein the memory cell is disposed adjacent the drain region so that the channel axis runs through the memory cell.
摘要翻译：一种包括晶体管（410）的器件，包括源极区（412）; 漏极区域（414）; 和沟道区（418），其中所述沟道区沿着沟道轴线（A）电连接所述源区和所述漏区。和存储单元（430），其中所述存储单元设置成与所述漏极区相邻，使得所述沟道轴线穿过所述存储单元。

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