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1. 发明申请

WO2017144599A1 POWER MODULE BASED ON MULTI-LAYER CIRCUIT BOARD 审中-公开
标题翻译：基于多层电路板的电源模块
公开(公告)号：WO2017144599A1
公开(公告)日：2017-08-31
申请号：PCT/EP2017/054208
申请日：2017-02-23
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： MOHN, Fabian , SCHUDERER, Jürgen , TRAUB, Felix
IPC分类号： H01L23/538 , H01L23/498 , H01L23/13 , H01L25/07 , H05K1/18 , H01L23/14
CPC分类号： H01L23/49822 , H01L23/13 , H01L23/142 , H01L23/5383 , H01L25/072 , H01L2224/0603 , H01L2224/40225 , H01L2224/48491 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/49433 , H01L2924/15153 , H01L2924/181 , H05K1/0204 , H05K1/0206 , H05K1/0263 , H05K1/183 , H05K3/0061 , H05K2201/10166 , H05K2201/10318
摘要： A power module (10) comprises at least one power semiconductor device (15a, 15b) with an electrical topcontact area (28b) on a top side; and a multi-layer circuit board (12) with multiple electrically conducting layers (16a, 16b, 18) which are separated by multiple electrically isolating layers (20), the electrically isolating layers (20) being laminated together with the electrically conducting layers (16a, 16b, 18); wherein the multi-layer circuit board (12) has at least one cavity (14), which is opened to a top side of the multi-layer circuit board (12), which cavity (14) reaches through at least two electrically conducting layers (16a, 16b, 18); wherein the power semiconductor device (15a, 15b) is attached with a bottom side to a bottom of the cavity (14); and wherein the power semiconductor device (15a, 15b) is electrically connected to a top side of the multi-layer circuit board (12) with a conducting member (26a, 26b) bonded to the top contact area (28b) and bonded to the top side of the multi-layer circuit board (12).
摘要翻译：功率模块（10）包括至少一个功率半导体器件（15a，15b），所述至少一个功率半导体器件（15a，15b）在顶侧上具有电顶端接触区域（28b）和具有由多个电隔离层（20）隔开的多个导电层（16a，16b，18）的多层电路板（12），所述电隔离层（20）与所述导电层 16a，16b，18）; 其中所述多层电路板（12）具有至少一个空腔（14），所述空腔（14）向所述多层电路板（12）的顶侧开放，所述空腔（14）通过至少两个导电层（16a，16b，18）; 其中，所述功率半导体器件（15a，15b）的底侧连接到所述腔体（14）的底部; 并且其中所述功率半导体器件（15a，15b）通过结合到所述顶部接触区域（28b）的导电构件（26a，26b）电连接到所述多层电路板（12）的顶侧，并且结合到所述多层电路板多层电路板（12）的顶侧。

2. 发明申请

WO2020173899A1 ELECTRIC POWER CONVERTER DEVICE WITH IMPROVED INTEGRATION OF COOLER FRAME 审中-公开
公开(公告)号：WO2020173899A1
公开(公告)日：2020-09-03
申请号：PCT/EP2020/054828
申请日：2020-02-25
申请人： AUDI AG , ABB SCHWEIZ AG
发明人： TRAUB, Felix , SCHUDERER, Jürgen , MOHN, Fabian , GRADINGER, Thomas , LUI, Chunlei
IPC分类号： H01L23/473
摘要： An electric power converter device (1) comprises a first power semiconductor module (100) and a frame (20) for a closed cooler. The first power semiconductor module (100) includes a first base plate (30) having a first main side (32), a second main side (33) opposite the first main side and a lateral side surface (34) extending along a circumferential edge of the first base plate (30) and connecting the first and the second main side. The frame (20) is attached to the second main side (33) of the first base plate (20). The first base plate (30) has a first step (35A) on the second main side (33) along the circumferential edge of the first base plate (30) to form a first recess (35) along the circumferential edge of the first base plate (30), in which first recess (35) a first portion (21) of the frame (20) is received.

3. 发明申请

WO2018202620A1 HALF-BRIDGE MODULE WITH COAXIAL ARRANGEMENT OF THE DC TERMINALS 审中-公开
公开(公告)号：WO2018202620A1
公开(公告)日：2018-11-08
申请号：PCT/EP2018/061027
申请日：2018-04-30
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： MOHN, Fabian , TRAUB, Felix , SCHUDERER, Jürgen
IPC分类号： H01L25/07 , H01L23/498 , H01L23/538
摘要： A half-bridge module (10) comprises a substrate (12) with a base metallization layer (14) divided into a first DC conducting area (16), a second DC conducting area (20) and an AC conducting area (18); at least one first power semiconductor switch chip (22) bonded to the first DC conducting area (16) and electrically interconnected with the AC conducting area (18); at least one second power semiconductor switch chip (22) bonded to the AC conducting area (18) and electrically interconnected with the second DC conducting area (20); and a coaxial terminal arrangement (35) comprising at least one inner DC terminal (38), at least one first outer DC terminal (36) and at least one second outer DC terminal (40); wherein the at least one inner DC terminal (38), the at least first outer DC terminal (36) and the at least one second outer DC terminal (40) protrude from the module (10) and are arranged in a row, such that the at least one inner DC terminal (38) is coaxially arranged between the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40); wherein the at least one inner DC terminal (38) is electrically connected to the second DC conducting area (20); wherein the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40) are electrically connected to the first DC conducting area (16); and wherein the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40) are electrically interconnected with an electrically conducting bridging element (52, 70) which is adapted for distributing at least a half of the load current between the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40).

4. 发明申请

WO2018109069A1 POWER SEMICONDUCTOR MODULE WITH LOW GATE PATH INDUCTANCE 审中-公开
公开(公告)号：WO2018109069A1
公开(公告)日：2018-06-21
申请号：PCT/EP2017/082777
申请日：2017-12-14
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： COTTET, Didier , TRAUB, Felix , SCHUDERER, Jürgen , APELSMEIER, Andreas , ASAM, Johann
IPC分类号： H01L23/498 , H01L25/07
摘要： A power semiconductor module (10), comprises a housing (60); a power semiconductor chip (14) within the housing (60); power terminals (24) protruding from the housing (60) and electrically interconnected with power electrodes (18) of the semiconductor chip (14); and auxiliary terminals (46) protruding from the housing (60) and electrically interconnected with a gate electrode (16) and one of the power electrodes (18); wherein three auxiliary terminals (46a, 46b) are arranged in a coaxial auxiliary terminal arrangement (52), which comprises an inner and two outer auxiliary terminals (46a, 46b), which are arranged on opposing sides of the inner auxiliary terminal (46a). The inner auxiliary terminal (46a) is electrically interconnected with the gate electrode (16) or one of the power electrodes (18) and the two outer auxiliary terminals (46b) are electrically connected with the other one of the gate electrode (16) and the one of the power electrodes (18).

5. 发明申请

WO2018096050A1 MANUFACTURING OF A POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：WO2018096050A1
公开(公告)日：2018-05-31
申请号：PCT/EP2017/080248
申请日：2017-11-23
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： MOHN, Fabian , LIU, Chunlei , SCHUDERER, Jürgen
IPC分类号： H01L23/495 , H01L23/498 , H01L21/56 , H01L25/07
摘要： A semi-manufactured power semiconductor module (10) comprises a substrate (12) for bonding at least one power semiconductor chip (22); a first leadframe (14) bonded to the substrate and providing power terminals (24); and a second leadframe (16) bonded to the substrate and providing auxiliary terminals (26); wherein the first leadframe (14) and/or the second leadframe (16) comprise an interlocking element (34) adapted for aligning the first leadframe (14) and the second leadframe (16) with respect to each other and/or with respect to a mold (40) for molding an encapsulation (38) around the substrate (12), the first leadframe (14) and the second leadframe (16).

6. 发明申请

WO2016188909A1 POWER SEMICONDUCTOR MODULE 审中-公开
标题翻译：功率半导体模块
公开(公告)号：WO2016188909A1
公开(公告)日：2016-12-01
申请号：PCT/EP2016/061450
申请日：2016-05-20
申请人： ABB SCHWEIZ AG
发明人： TRAUB, Felix , MOHN, Fabian , SCHUDERER, Jürgen , KEARNEY, Daniel , KICIN, Slavo
IPC分类号： H01L23/538 , H01L23/64 , H01L25/07
CPC分类号： H01L23/5385 , H01L23/3735 , H01L23/49811 , H01L23/645 , H01L25/072 , H01L29/00 , H01L2224/48091 , H01L2224/48137 , H01L2224/49111 , H01L2924/19107 , H01L2924/00014
摘要： The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor (22) and at least one power semiconductor diode (24), wherein at least a first substrate (26) is provided for carrying the power semiconductor transistor (22) in a first plane (44), the first plane lying parallel to the plane of the substrate (26), characterized in that the power semiconductor diode (24) is provided in a second plane (46), wherein the first plane (44) is positioned between the substrate (26) and the second plane (46) in a direction normal to the first plane (44) and wherein the first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44). The first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44), whereby the first substrate (26) is based on a direct bonded copper substrate and the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a layer of a printed circuit board (PCB) is provided for carrying the diode (24). Alternatively, the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a foil is provided for carrying the diode (24), wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode (24). Such a power semiconductor module provides a low stray inductance and/or may be built easily.
摘要翻译：本发明涉及功率半导体模块，其包括至少两个功率半导体器件，其中所述至少两个功率半导体器件包括至少一个功率半导体晶体管（22）和至少一个功率半导体二极管（24），其中至少提供第一衬底（26），用于在第一平面（44）中承载功率半导体晶体管（22），该第一平面平行于衬底（26）的平面，其特征在于功率半导体二极管（24）设置在第二平面（46）中，其中所述第一平面（44）在垂直于所述第一平面（44）的方向上位于所述基板（26）和所述第二平面（46）之间，并且其中所述第一平面）在垂直于第一平面（44）的方向上与第二平面（46）间隔开。第一平面（44）在垂直于第一平面（44）的方向上与第二平面（46）间隔开，由此第一基底（26）基于直接键合的铜基底和第一基底（26），是用于承载晶体管（22）的直接接合的铜基板，其上设置有用于承载二极管（24）的印刷电路板（PCB）层的第一基板（26）。或者，第一衬底（26）是用于承载晶体管（22）的直接键合铜衬底，第一衬底（26）上设置有用于承载二极管（24）的箔，其中箔包括电绝缘主体主体和设置在其上的用于承载二极管（24）的导电结构。这样的功率半导体模块提供了低杂散电感和/或可容易地构建。

7. 发明申请

WO2017076659A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件和用于制造功率半导体器件的方法
公开(公告)号：WO2017076659A1
公开(公告)日：2017-05-11
申请号：PCT/EP2016/075266
申请日：2016-10-20
申请人： ABB SCHWEIZ AG
发明人： DONZEL, Lise , SCHUDERER, Jürgen , DOBRZYNSKA, Jagoda , VOBECKY, Jan
IPC分类号： H01L23/31 , H01L29/06
CPC分类号： H01L29/0661 , H01L23/3185
摘要： The present invention relates to a power semiconductor device, comprising a substrate (12) having a first side (14) and a second side (16), the first side (14) and the second side (16) being located opposite to each other, wherein the first side (14) comprises a 5 cathode (18) and wherein the second side (14) comprises an anode (20), wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side (14) and the second side, characterized in that the junction termination is coated by a passivating coating (26), the passivating coating (26) comprising at least one material selected from the group 0 consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles. A device (10) as described above thus addresses issues of passivation of junction terminations and thus prevents or at least reduces the danger of fatal defects such as unstable device operation caused by changes in film properties, instability, water permeability, permeability of movable ions such as sodium, 5 pinholes and cracks, and aluminum metal disconnection or corrosion due to degradation and stress.
摘要翻译：本发明涉及一种功率半导体器件，其包括具有第一侧（14）和第二侧（16）的衬底（12），所述第一侧（14）和所述第二侧（，其中所述第一侧（14）包括阴极（18），并且其中所述第二侧（14）包括阳极（20），其中提供了p / n结的结终端在所述衬底的至少一个表面上，优选在所述第一侧面（14）和所述第二侧面中的至少一个上，其特征在于，所述结终端被钝化涂层（26）涂覆，所述钝化涂层（26）选自由无机 - 有机复合材料，聚对二甲苯和包含聚合物颗粒的酚醛树脂组成的组0中的至少一种材料。因此，如上所述的器件（10）解决了接线端子钝化的问题并且因此防止或至少减少了致命缺陷的危险，例如由膜性质，不稳定性，透水性，可移动离子渗透性等引起的不稳定器件操作作为钠，5个针孔和裂缝，以及由于退化和压力导致铝金属脱落或腐蚀。

8. 发明申请

WO2018001983A1 COOLED ELECTRONICS PACKAGE WITH STACKED POWER ELECTRONICS COMPONENTS 审中-公开
标题翻译：带堆叠功率电子元件的冷却式电子产品包装
公开(公告)号：WO2018001983A1
公开(公告)日：2018-01-04
申请号：PCT/EP2017/065743
申请日：2017-06-26
申请人： ABB SCHWEIZ AG
发明人： KEARNEY, Daniel , SCHUDERER, Jürgen , KICIN, Slavo , DUARTE, Liliana
IPC分类号： H01L23/473 , H05K1/02
摘要： An electronics package (10) comprises an electrically conducting support layer (20b); at least one electrically conducting outer layer (20a, 20c); at least two power electronics components (14) arranged on different sides of the support layer (20b) and electrically interconnected with the support layer (20b) and with the at least one outer layer (20a, 20b); an isolation material (18), in which the support layer (20b) and the at least two power electronics components (14) are embedded, wherein the support layer (20b) and the at least one outer layer (20a, 20c) are laminated together with the isolation material (18); and a cooling channel (26) for conducting a cooling fluid through the electronics package (10), wherein the cooling channel (26) runs between the at least two power electronics components (14) through the support layer (20b).
摘要翻译：电子封装（10）包括导电支撑层（20b）;以及电子部件至少一个导电外层（20a，20c）; 至少两个电力电子部件（14），其布置在所述支撑层（20b）的不同侧上并且与所述支撑层（20b）以及所述至少一个外层（20a，20b）电互连; 其中嵌入有所述支撑层（20b）和所述至少两个电力电子部件（14）的隔离材料（18），其中所述支撑层（20b）和所述至少一个外层（20a，20c）被层压与隔离材料（18）一起; 和用于引导冷却流体通过电子组件（10）的冷却通道（26），其中冷却通道（26）通过支撑层（20b）在至少两个功率电子部件（14）之间延伸。

9. 发明申请

WO2018141867A1 POWER SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE 审中-公开
公开(公告)号：WO2018141867A1
公开(公告)日：2018-08-09
申请号：PCT/EP2018/052559
申请日：2018-02-01
申请人： ABB SCHWEIZ AG
发明人： LIU, Chunlei , SCHUDERER, Jürgen , BREM, Franziska , RAHIMO, Munaf , STEIMER, Peter Karl , DUGAL, Franc
IPC分类号： H01L23/051 , H01L23/535 , H01L23/62 , H01L25/07 , H01L29/16 , H01L23/00
摘要： A power semiconductor module (10) comprises a base plate (12); a Si chip (16a) comprising a Si substrate, the Si chip (16a) attached to the base plate (12); a first metal preform (22a) pressed with a first press pin (24a) against the Si chip (16a); a wide bandgap material chip (16b) comprising a wide bandgap substrate and a semiconductor switch (28b) provided in the wide bandgap substrate, the wide bandgap material chip (16b) attached to the base plate (12); and a second metal preform (22b) pressed with a second press pin (24b) against the wide bandgap material chip (16b); wherein the Si chip (16a) and the wide bandgap material chip (16b) are connected in parallel via the base plate (12) and via the first press pin (24a) and the second press pin (24b); wherein the first metal preform (22a) is adapted for forming a conducting path through the Si chip (16a), when heated by an overcurrent; and wherein the second metal preform (22b) is adapted for forming an temporary conducting path through the wide bandgap material chip (16b) or an open circuit, when heated by an overcurrent.

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