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1. 发明申请

WO2018065317A1 SIC-ON-SI-BASED SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE 审中-公开
标题翻译：基于SIC-ON-SI的半导体模块具有短路故障模式
公开(公告)号：WO2018065317A1
公开(公告)日：2018-04-12
申请号：PCT/EP2017/074804
申请日：2017-09-29
申请人： ABB SCHWEIZ AG
发明人： LIU, Chunlei , RAHIMO, Munaf , STEIMER, Peter
IPC分类号： H01L23/62 , H01L23/051 , H01L25/07
CPC分类号： H01L23/34 , H01L23/051 , H01L23/492 , H01L23/5252 , H01L23/62 , H01L24/72 , H01L25/072
摘要： A semiconductor module (10) comprises a semiconductor chip (12) comprising a Si base layer (14) and a SiC epitaxy layer (16) on the Si base layer (14), the SiC epitaxy layer (16) comprising a semiconductor element (17); an electrical conducting top layer (e.g. Mo) (24) for providing an electrical contact of the semiconductor module (10) on a side of the SiC epitaxy layer (16); an electrical conducting bottom layer (e.g. Mo) (22) for providing an electrical contact of the semiconductor module (10) on a side of the Si base layer (14); and a failure mode layer (26, 26a) in contact with the SiC epitaxy layer (16) and arranged between the top layer (24) and the bottom layer (22), the failure mode layer (26, 26a) comprising a metal material (e.g. Al, Cu, Ag, Au) (27) adapted for forming a eutectic alloy with the Si base layer (14), to short-circuit the semiconductor module (10). The semiconductor module (10) may also comprise a second failure mode layer (26, 26b) in contact with the Si base layer (14). The second failure mode layer (26, 26b) may be coated to a core (30) of the bottom layer (22), in which case the core (30) is made of Al-graphite (aluminium graphite composite), AlSiC (aluminium silicon carbide composite) or AlSip (aluminum matrix composite reinforced with high amount of silicon particles).
摘要翻译：半导体模块（10）包括在Si基底层（14）上包括Si基底层（14）和SiC外延层（16）的半导体芯片（12），SiC外延层（16），包括半导体元件（17）; 用于在SiC外延层（16）的一侧上提供半导体模块（10）的电接触的导电顶层（例如，Mo）（24）; 用于在Si基层（14）的一侧上提供半导体模块（10）的电接触的导电底层（例如Mo）（22）; 和与所述SiC外延层（16）接触并布置在所述顶层（24）和所述底层（22）之间的故障模式层（26,26a），所述故障模式层（26,26a）包括金属材料（例如Al，Cu，Ag，Au）（27），用于与Si基层（14）形成共晶合金，以使半导体模块（10）短路。半导体模块（10）还可以包括与Si基极层（14）接触的第二失效模式层（26,26b）。第二破坏模式层（26,26b）可以被涂覆到底层（22）的芯部（30），在这种情况下，芯部（30）由Al-石墨（铝石墨复合材料），AlSiC 碳化硅复合材料）或AlSip（用大量硅颗粒增强的铝基复合材料）。

2. 发明申请

WO2017157486A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2017157486A1
公开(公告)日：2017-09-21
申请号：PCT/EP2016/075970
申请日：2016-10-27
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： LIU, Chunlei , MOHN, Fabian , BREM, Franziska
IPC分类号： H01L23/49 , H01L23/492
摘要： A semiconductor device (28) comprises a semiconductor element (10) with a power electrode area (16), a control electrode area (18) and an elevated control electrode structure (20) on one side, wherein the elevated control electrode structure (20) is interconnected with the control electrode area (18) and protrudes the power electrode area (16); and a grooved plate (30), which is bonded with a grooved side (34) to the power electrode area (16); wherein the grooved plate (30) has at least one groove (36) in the grooved side (34), in which at least a part of the control electrode structure (20) is accommodated, whereby the grooved plate (30) is sintered via a sintering preform (40) interpositioned between the grooved plate (30) and the semiconductor element (10) to the power electrode area (16), such that the sintering preform (40) covers the elevated control electrode structure (20).
摘要翻译：半导体器件（28）包括在一侧具有功率电极区域（16），控制电极区域（18）和升高的控制电极结构（20）的半导体元件（10）其中所述升高的控制电极结构（20）与所述控制电极区域（18）互连并且突出所述功率电极区域（16）; 和沟槽板（30），所述沟槽板（30）与沟槽侧（34）结合到所述功率电极区域（16）; 其特征在于，所述开槽板（30）在所述开槽侧（34）中具有至少一个凹槽（36），所述控制电极结构（20）的至少一部分容纳在所述凹槽中，其中所述开槽板（30）在沟槽板（30）与半导体元件（10）之间插入功率电极区域（16）的烧结预型件（40），使得烧结预型件（40）覆盖升高的控制电极结构（20） p>

3. 发明申请

WO2018096050A1 MANUFACTURING OF A POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：WO2018096050A1
公开(公告)日：2018-05-31
申请号：PCT/EP2017/080248
申请日：2017-11-23
申请人： ABB SCHWEIZ AG , AUDI AG
发明人： MOHN, Fabian , LIU, Chunlei , SCHUDERER, Jürgen
IPC分类号： H01L23/495 , H01L23/498 , H01L21/56 , H01L25/07
摘要： A semi-manufactured power semiconductor module (10) comprises a substrate (12) for bonding at least one power semiconductor chip (22); a first leadframe (14) bonded to the substrate and providing power terminals (24); and a second leadframe (16) bonded to the substrate and providing auxiliary terminals (26); wherein the first leadframe (14) and/or the second leadframe (16) comprise an interlocking element (34) adapted for aligning the first leadframe (14) and the second leadframe (16) with respect to each other and/or with respect to a mold (40) for molding an encapsulation (38) around the substrate (12), the first leadframe (14) and the second leadframe (16).

4. 发明申请

WO2019197304A1 MATERIAL REDUCED METALLIC PLATE ON POWER SEMICONDUCTOR CHIP 审中-公开
公开(公告)号：WO2019197304A1
公开(公告)日：2019-10-17
申请号：PCT/EP2019/058748
申请日：2019-04-08
申请人： ABB SCHWEIZ AG
发明人： MOHN, Fabian , SOKOLOV, Alexey , LIU, Chunlei
IPC分类号： H01L21/60
摘要： A power semiconductor module (10) comprises a substrate (12) with a metallization layer (18); a power semiconductor chip (14) bonded to the metallization layer (18) of the substrate (12); and a metallic plate (24) bonded to the power semiconductor chip (14) opposite to the substrate (12). The metallic plate (24) has a border (36), which is structured in such a way that the metallic plate (24) has less metal material per area at the border (36) as compared to a central part (34) of the metallic plate (24).

5. 发明申请

WO2018197363A1 POWER MODULE BASED ON NORMALLY-ON SEMICONDUCTOR SWITCHES 审中-公开
公开(公告)号：WO2018197363A1
公开(公告)日：2018-11-01
申请号：PCT/EP2018/060227
申请日：2018-04-20
申请人： ABB SCHWEIZ AG
发明人： DROFENIK, Uwe , CANALES, Francisco , LIU, Chunlei , BREM, Franziska
IPC分类号： H02M1/32
摘要： A power module (10) comprises a plurality of normally-on semiconductor switches (14) based on a wide bandgap substrate, the normally-on semiconductor switches (14) connected in parallel; and a balancing unit (24) comprising a capacitor (32) and a balancing semiconductor switch (34) connected in series, which are connected in parallel to the normally-on semiconductor switches (14).

6. 发明申请

WO2018141867A1 POWER SEMICONDUCTOR MODULE WITH SHORT CIRCUIT FAILURE MODE 审中-公开
公开(公告)号：WO2018141867A1
公开(公告)日：2018-08-09
申请号：PCT/EP2018/052559
申请日：2018-02-01
申请人： ABB SCHWEIZ AG
发明人： LIU, Chunlei , SCHUDERER, Jürgen , BREM, Franziska , RAHIMO, Munaf , STEIMER, Peter Karl , DUGAL, Franc
IPC分类号： H01L23/051 , H01L23/535 , H01L23/62 , H01L25/07 , H01L29/16 , H01L23/00
摘要： A power semiconductor module (10) comprises a base plate (12); a Si chip (16a) comprising a Si substrate, the Si chip (16a) attached to the base plate (12); a first metal preform (22a) pressed with a first press pin (24a) against the Si chip (16a); a wide bandgap material chip (16b) comprising a wide bandgap substrate and a semiconductor switch (28b) provided in the wide bandgap substrate, the wide bandgap material chip (16b) attached to the base plate (12); and a second metal preform (22b) pressed with a second press pin (24b) against the wide bandgap material chip (16b); wherein the Si chip (16a) and the wide bandgap material chip (16b) are connected in parallel via the base plate (12) and via the first press pin (24a) and the second press pin (24b); wherein the first metal preform (22a) is adapted for forming a conducting path through the Si chip (16a), when heated by an overcurrent; and wherein the second metal preform (22b) is adapted for forming an temporary conducting path through the wide bandgap material chip (16b) or an open circuit, when heated by an overcurrent.

7. 发明申请

WO2018141811A1 POWER SEMICONDUCTOR DEVICE WITH ACTIVE SHORT CIRCUIT FAILURE MODE 审中-公开
公开(公告)号：WO2018141811A1
公开(公告)日：2018-08-09
申请号：PCT/EP2018/052434
申请日：2018-01-31
申请人： ABB SCHWEIZ AG
发明人： LIU, Chunlei , DUGAL, Franc , RAHIMO, Munaf , STEIMER, Peter Karl
IPC分类号： H01L23/62 , H01L25/07 , H01L29/16 , H01L23/051 , H01L23/535
摘要： A power semiconductor device (10) comprises a Si chip (12) providing a Si switch (14) and a wide bandgap material chip (16) providing a wide bandgap material switch (18), wherein the Si switch (14) and the wide bandgap material switch (18) are electrically connected in parallel. A method for controlling a power semiconductor device (10) comprises: during a normal operation mode, controlling at least the wide bandgap material switch (18) for switching a current through the power semiconductor device (10) by applying corresponding gate signals to at least the wide bandgap material switch (18); sensing a failure in the power semiconductor device (10); and, in the case of a sensed failure, controlling the Si switch (14) by applying a gate signal, such that a current is generated in the Si chip (12) heating the Si chip (12) to a temperature forming a permanent conducting path through the Si chip (12).

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