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1. 发明申请

WO2016188909A1 POWER SEMICONDUCTOR MODULE 审中-公开
标题翻译：功率半导体模块
公开(公告)号：WO2016188909A1
公开(公告)日：2016-12-01
申请号：PCT/EP2016/061450
申请日：2016-05-20
申请人： ABB SCHWEIZ AG
发明人： TRAUB, Felix , MOHN, Fabian , SCHUDERER, Jürgen , KEARNEY, Daniel , KICIN, Slavo
IPC分类号： H01L23/538 , H01L23/64 , H01L25/07
CPC分类号： H01L23/5385 , H01L23/3735 , H01L23/49811 , H01L23/645 , H01L25/072 , H01L29/00 , H01L2224/48091 , H01L2224/48137 , H01L2224/49111 , H01L2924/19107 , H01L2924/00014
摘要： The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor (22) and at least one power semiconductor diode (24), wherein at least a first substrate (26) is provided for carrying the power semiconductor transistor (22) in a first plane (44), the first plane lying parallel to the plane of the substrate (26), characterized in that the power semiconductor diode (24) is provided in a second plane (46), wherein the first plane (44) is positioned between the substrate (26) and the second plane (46) in a direction normal to the first plane (44) and wherein the first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44). The first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44), whereby the first substrate (26) is based on a direct bonded copper substrate and the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a layer of a printed circuit board (PCB) is provided for carrying the diode (24). Alternatively, the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a foil is provided for carrying the diode (24), wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode (24). Such a power semiconductor module provides a low stray inductance and/or may be built easily.
摘要翻译：本发明涉及功率半导体模块，其包括至少两个功率半导体器件，其中所述至少两个功率半导体器件包括至少一个功率半导体晶体管（22）和至少一个功率半导体二极管（24），其中至少提供第一衬底（26），用于在第一平面（44）中承载功率半导体晶体管（22），该第一平面平行于衬底（26）的平面，其特征在于功率半导体二极管（24）设置在第二平面（46）中，其中所述第一平面（44）在垂直于所述第一平面（44）的方向上位于所述基板（26）和所述第二平面（46）之间，并且其中所述第一平面）在垂直于第一平面（44）的方向上与第二平面（46）间隔开。第一平面（44）在垂直于第一平面（44）的方向上与第二平面（46）间隔开，由此第一基底（26）基于直接键合的铜基底和第一基底（26），是用于承载晶体管（22）的直接接合的铜基板，其上设置有用于承载二极管（24）的印刷电路板（PCB）层的第一基板（26）。或者，第一衬底（26）是用于承载晶体管（22）的直接键合铜衬底，第一衬底（26）上设置有用于承载二极管（24）的箔，其中箔包括电绝缘主体主体和设置在其上的用于承载二极管（24）的导电结构。这样的功率半导体模块提供了低杂散电感和/或可容易地构建。

2. 发明申请

WO2020114660A1 HYBRID SHORT CIRCUIT FAILURE MODE PREFORM FOR POWER SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：WO2020114660A1
公开(公告)日：2020-06-11
申请号：PCT/EP2019/078249
申请日：2019-10-17
申请人： ABB SCHWEIZ AG
发明人： COTTET, Didier , KICIN, Slavo
IPC分类号： H01L23/62 , H01L25/07
摘要： A power semiconductor module comprises a base plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

3. 发明申请

WO2018001983A1 COOLED ELECTRONICS PACKAGE WITH STACKED POWER ELECTRONICS COMPONENTS 审中-公开
标题翻译：带堆叠功率电子元件的冷却式电子产品包装
公开(公告)号：WO2018001983A1
公开(公告)日：2018-01-04
申请号：PCT/EP2017/065743
申请日：2017-06-26
申请人： ABB SCHWEIZ AG
发明人： KEARNEY, Daniel , SCHUDERER, Jürgen , KICIN, Slavo , DUARTE, Liliana
IPC分类号： H01L23/473 , H05K1/02
摘要： An electronics package (10) comprises an electrically conducting support layer (20b); at least one electrically conducting outer layer (20a, 20c); at least two power electronics components (14) arranged on different sides of the support layer (20b) and electrically interconnected with the support layer (20b) and with the at least one outer layer (20a, 20b); an isolation material (18), in which the support layer (20b) and the at least two power electronics components (14) are embedded, wherein the support layer (20b) and the at least one outer layer (20a, 20c) are laminated together with the isolation material (18); and a cooling channel (26) for conducting a cooling fluid through the electronics package (10), wherein the cooling channel (26) runs between the at least two power electronics components (14) through the support layer (20b).
摘要翻译：电子封装（10）包括导电支撑层（20b）;以及电子部件至少一个导电外层（20a，20c）; 至少两个电力电子部件（14），其布置在所述支撑层（20b）的不同侧上并且与所述支撑层（20b）以及所述至少一个外层（20a，20b）电互连; 其中嵌入有所述支撑层（20b）和所述至少两个电力电子部件（14）的隔离材料（18），其中所述支撑层（20b）和所述至少一个外层（20a，20c）被层压与隔离材料（18）一起; 和用于引导冷却流体通过电子组件（10）的冷却通道（26），其中冷却通道（26）通过支撑层（20b）在至少两个功率电子部件（14）之间延伸。

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