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1. 发明申请

WO2022261223A1 APPARATUS, SYSTEM, AND METHOD FOR CONFIGURING A CONFIGURABLE COMBINED PRIVATE AND SHARED CACHE 审中-公开
公开(公告)号：WO2022261223A1
公开(公告)日：2022-12-15
申请号：PCT/US2022/032694
申请日：2022-06-08
申请人： AMPERE COMPUTING LLC
发明人： SHANNON, Richard James , JOURDAN, Stephan Jean , ERLER, Matthew Robert , BENDT, Jared Eric
IPC分类号： G06F12/084 , G06F12/0846
摘要： Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.

2. 发明申请

WO2019201657A1 ACCELERATOR AND SYSTEM FOR ACCELERATING OPERATIONS 审中-公开
公开(公告)号：WO2019201657A1
公开(公告)日：2019-10-24
申请号：PCT/EP2019/058871
申请日：2019-04-09
申请人： AIMOTIVE KFT.
发明人： NAGY, Gyula , FEHÉR, Márton
IPC分类号： G06F12/0846 , G06N3/063 , G06F9/50 , G06F12/0875 , G06N3/04
摘要： An accelerator and a system for accelerating operations are disclosed. A respective apparatus comprises an interface configured to couple the apparatus to an interconnect, a plurality of processing modules, each configured to process data, a control module configured to control processing of each of the plurality of processing modules, and a cache module configured to store at least a portion of data processed by at least one of the plurality of processing modules. Each processing module further includes a processing core configured to process data by performing an operation on the data using a plurality of processing elements, an input control unit configured to retrieve data via the interface and data stored in the cache module and to provide the retrieved data to the processing core, and an output control unit configured to provide data processed by the processing core to the interface and the cache module.

3. 发明申请

WO01044948A1 DATA PROCESSOR WITH CACHE 审中-公开
标题翻译：数据处理器与缓存
公开(公告)号：WO01044948A1
公开(公告)日：2001-06-21
申请号：PCT/EP2000/012231
申请日：2000-12-04
IPC分类号： G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F12/08
CPC分类号： G06F12/0848 , G06F12/0862 , G06F12/0864
摘要： A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an "as needed" basis and the remaining cache memory locations can be used for non-stream addresses.
摘要翻译：数据处理器具有具有关联存储器的高速缓冲存储器，用于存储相应主存储器地址和高速缓冲存储器位置之间的至少第一和第二组关联。至少一个高速缓冲存储器位置可动态地分配给不同的组，以用于所分配组的关联。当指令指示主存储器地址时，选择组以找到与主存储器地址相关联的高速缓冲存储器位置。在一个实施例中，处理器从迭代计算的主存储器地址访问地址流。每个流都具有自己的一组来自流的与地址分配的缓冲存储器位置的分组关联。剩余的高速缓存存储器位置通过集合关联映射来访问。因此，可以在“根据需要”的基础上将高速缓冲存储器位置分配给不同的流，并且剩余的高速缓冲存储器位置可用于非流地址。

4. 发明申请

WO2021262354A1 CONFIGURING CACHE POLICIES FOR A CACHE BASED ON COMBINED CACHE POLICY TESTING 审中-公开
公开(公告)号：WO2021262354A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/033434
申请日：2021-05-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KELLEY, John , MOYER, Paul
IPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817 , G06F12/0846 , G06F12/0871 , G06F11/30 , G06F11/076 , G06F11/3037 , G06F11/3409 , G06F12/0891
摘要： An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.

5. 发明申请

WO2020167359A1 SYSTEM-LEVEL CACHE 审中-公开
公开(公告)号：WO2020167359A1
公开(公告)日：2020-08-20
申请号：PCT/US2019/063414
申请日：2019-11-26
申请人： GOOGLE LLC
发明人： CHAMARTY, Vinod , MA, Xiaoyu , YOON, Hongil , PFLEDERER, Keith Robert , LIAO, Weiping , DODGE, Benjamin , MEIXNER, Albert , KNIES, Allan Douglas , GULATI, Manu , THAKUR, Rahul Jagdish , REDGRAVE, Jason Rupert
IPC分类号： G06F12/084 , G06F12/0846
摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

6. 发明申请

WO2020146214A1 COPROCESSOR OPERATION BUNDLING 审中-公开
公开(公告)号：WO2020146214A1
公开(公告)日：2020-07-16
申请号：PCT/US2020/012232
申请日：2020-01-03
申请人： APPLE INC.
发明人： KESIRAJU, Aditya , FEERO, Brett S. , GUPTA, Nikhil , GAUTAM, Viney
IPC分类号： G06F12/0846 , G06F12/084
摘要： In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

7. 发明申请

WO2020132434A1 SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE 审中-公开
公开(公告)号：WO2020132434A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/067838
申请日：2019-12-20
申请人： MICRON TECHNOLOGY, INC.
发明人： YUDANOV, Dmitri, A. , JAIN, Shanky, Kumar
IPC分类号： G06F12/0871 , G06F12/0846 , G06F12/1009 , G06F12/1027 , G06F12/0875
摘要： Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

8. 发明申请

WO2020123343A1 CACHE FOR STORING REGIONS OF DATA 审中-公开
公开(公告)号：WO2020123343A1
公开(公告)日：2020-06-18
申请号：PCT/US2019/065155
申请日：2019-12-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel, H.
IPC分类号： G06F12/0802 , G06F12/02 , G06F12/0811 , G06F12/0846 , G06F12/0862 , G06F12/0897
摘要： Systems, apparatuses, and methods for efficiently performing memory accesses in a computing system are disclosed. A computing system includes one or more clients, a communication fabric and a last-level cache implemented with low latency, high bandwidth memory. The cache controller for the last-level cache determines a range of addresses corresponding to a first region of system memory with a copy of data stored in a second region of the last-level cache. The cache controller sends a selected memory access request to system memory when the cache controller determines a request address of the memory access request is not within the range of addresses. The cache controller services the selected memory request by accessing data from the last-level cache when the cache controller determines the request address is within the range of addresses.

9. 发明申请

WO2019138206A1 SPECULATIVE CACHE STORAGE REGION 审中-公开
公开(公告)号：WO2019138206A1
公开(公告)日：2019-07-18
申请号：PCT/GB2018/052449
申请日：2018-08-30
申请人： ARM LIMITED
发明人： GRISENTHWAITE, Richard Roy
IPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126 , G06F12/0804 , G06F12/0846 , G06F12/0864 , G06F12/14 , G06F12/0862 , G06F9/38 , G06F21/57 , G06F21/75 , G06F12/0815
摘要： An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions;a main cache storage region (30);a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative.This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses.

10. 发明申请

WO2023066836A1 TRANSPARENT INTERLEAVING OF COMPRESSED CACHE LINES 审中-公开
公开(公告)号：WO2023066836A1
公开(公告)日：2023-04-27
申请号：PCT/EP2022/078771
申请日：2022-10-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： ABALI, Bulent , BUYUKTOSUNOGLU, Alper , PRASKY, Brian , BERGER, Deanna
IPC分类号： G06F12/0846 , G06F12/0871 , G06F12/0886 , G06F12/0895
摘要： Low latency in a non-uniform cache access ("NUCA") cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.

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