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1. 发明申请

WO2012051120A3 TWO SILICON-CONTAINING PRECURSORS FOR GAPFILL ENHANCING DIELECTRIC LINER 审中-公开
公开(公告)号：WO2012051120A3
公开(公告)日：2012-04-19
申请号：PCT/US2011/055641
申请日：2011-10-10
申请人： APPLIED MATERIALS, INC. , BHATIA, Sidharth , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar
发明人： BHATIA, Sidharth , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar
IPC分类号： H01L21/316 , H01L21/762
摘要： Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si-O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si-C bond and a Si-N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si-O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

2. 发明申请

WO2013070436A1 METHODS OF REDUCING SUBSTRATE DISLOCATION DURING GAPFILL PROCESSING 审中-公开
标题翻译：减少加工过程中底板偏差的方法
公开(公告)号：WO2013070436A1
公开(公告)日：2013-05-16
申请号：PCT/US2012/061726
申请日：2012-10-24
申请人： APPLIED MATERIALS, INC.
发明人： HONG, Sukwon , HAMANA, Hiroshi , LIANG, Jingmei
IPC分类号： H01L21/31
CPC分类号： H01L21/306 , H01L21/02164 , H01L21/02274 , H01L21/02326 , H01L21/02337 , H01L21/76229
摘要： Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.
摘要翻译：描述了在不对称沟槽之间减少半导体衬底中的位错的方法。所述方法可以包括蚀刻半导体衬底上的多个沟槽，并且可以包括由衬底的未蚀刻部分分开的不相等宽度的两个相邻沟槽。所述方法可以包括在基底上形成电介质材料层。介电材料可以在分离两个沟槽的衬底的未蚀刻部分的两侧上在相邻的基本相当的高度的沟槽中形成层。所述方法可以包括使介电材料层致密化，使得在不同宽度的两个沟槽内的致密电介质对基板的未蚀刻部分施加基本相似的应力。

3. 发明申请

WO2010080216A3 PRECURSOR ADDITION TO SILICON OXIDE CVD FOR IMPROVED LOW TEMPERATURE GAPFILL 审中-公开
公开(公告)号：WO2010080216A3
公开(公告)日：2010-07-15
申请号：PCT/US2009/065181
申请日：2009-11-19
申请人： APPLIED MATERIALS, INC. , VENKATARAMAN, Shankar , HAMANA, Hiroshi , HERNANDEZ, Manuel, A. , INGLE, Nitin, K. , GEE, Paul, Edward
发明人： VENKATARAMAN, Shankar , HAMANA, Hiroshi , HERNANDEZ, Manuel, A.
IPC分类号： H01L21/205 , H01L21/31 , H01L21/76
摘要： Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material.

4. 发明申请

WO2011129957A2 PREFERENTIAL DIELECTRIC GAPFILL 审中-公开
标题翻译：优选电介质
公开(公告)号：WO2011129957A2
公开(公告)日：2011-10-20
申请号：PCT/US2011/029428
申请日：2011-03-22
申请人： APPLIED MATERIALS, INC. , KWESKIN, Sasha , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
发明人： KWESKIN, Sasha , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
IPC分类号： H01L21/316 , H01L21/31
CPC分类号： H01L21/76229 , H01L21/67017
摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
摘要翻译：本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分。狭窄的沟槽用致密材料填充，而开放区域被一层致密材料和更多孔的材料覆盖。此时可以通过湿蚀刻在较宽的沟槽中去除介电材料，同时保留窄沟槽中的致密材料。

5. 发明申请

WO2014149862A1 PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING 审中-公开
标题翻译：加工系统和方法
公开(公告)号：WO2014149862A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/021246
申请日：2014-03-06
申请人： APPLIED MATERIALS, INC.
发明人： WANG, Anchuan , CHEN, Xinglong , LI, Zihui , HAMANA, Hiroshi , CHEN, Zhijun , HSU, Ching-Mei , HUANG, Jiayin , INGLE, Nitin K. , LUBOMIRSKY, Dmitry , VENKATARAMAN, Shankar , THAKUR, Randhir
IPC分类号： H01L21/02
CPC分类号： H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
摘要： Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
摘要翻译：提供系统，室和过程以控制由水分污染引起的过程缺陷。这些系统可以提供腔室的配置，以在真空或受控环境中执行多个操作。腔室可以包括在组合腔室设计中提供附加处理能力的构造。这些方法可以提供由系统工具执行的蚀刻工艺可能引起的老化缺陷的限制，预防和校正。

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