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1. 发明申请

WO2013040335A1 EFFICIENT NON-VOLATILE READ CACHE FOR STORAGE SYSTEM 审中-公开
标题翻译：有效的非易失性存储系统读取缓存
公开(公告)号：WO2013040335A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/055382
申请日：2012-09-14
申请人： APPLE INC. , MAISLOS, Ariel , MEIR, Avraham Poza
发明人： MAISLOS, Ariel , MEIR, Avraham Poza
IPC分类号： G06F13/00
CPC分类号： G06F12/0868 , G06F12/0246 , G06F2212/7201
摘要： A method includes, in a storage device that includes a non-volatile memory having a physical storage space, receiving data items associated with respective logical addresses assigned in a logical address space that is larger than the physical storage space. The logical addresses of the data items are translated into respective physical storage locations in the non-volatile memory. The data items are stored in the respective physical storage locations.
摘要翻译：一种方法包括在包括具有物理存储空间的非易失性存储器的存储设备中，接收与分配在大于物理存储空间的逻辑地址空间中的相应逻辑地址相关联的数据项。数据项的逻辑地址被转换成非易失性存储器中的相应物理存储位置。数据项存储在相应的物理存储位置。

2. 发明申请

WO2007132456A2 MEMORY DEVICE WITH ADAPTIVE CAPACITY 审中-公开
标题翻译：具有适应能力的存储器件
公开(公告)号：WO2007132456A2
公开(公告)日：2007-11-22
申请号：PCT/IL2007/000579
申请日：2007-05-10
申请人： ANOBIT TECHNOLOGIES LTD. , SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
发明人： SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
IPC分类号： H04N7/14
CPC分类号： G11C16/349 , G06F2212/7205 , G06F2212/7206 , G11C11/56 , G11C11/5607 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C11/5657 , G11C11/5671 , G11C11/5678 , G11C27/005 , G11C2211/5621 , G11C2211/5641
摘要： A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.
摘要翻译：一种用于在包括多个模拟存储器单元（32）的存储器（28）中的数据存储的方法包括估计模拟存储器单元的各个可实现的存储容量。根据估计的可实现的容量，为存储器单元分配相应的存储配置，其定义要存储在存储器单元中的数据量。数据根据相应的分配的存储配置存储在存储器单元中。在存储器已经安装在主机系统中并用于在主机系统中存储数据之后，重新估计模拟存储器单元的可实现的存储容量。存储配置根据重新估计的可实现容量进行修改。

3. 发明申请

WO2006048859A3 METHODS AND SYSTEMS FOR BANDWIDTHS DOUBLING IN AN ETHERNET PASSIVE OPTICAL NETWORK 审中-公开
公开(公告)号：WO2006048859A3
公开(公告)日：2006-05-11
申请号：PCT/IL2005/001061
申请日：2005-10-02
申请人： PASSAVE LTD. , HARAN, Onn , MAISLOS, Ariel
发明人： HARAN, Onn , MAISLOS, Ariel
IPC分类号： H04B10/20 , H04J14/00
摘要： Systems and methods for bandwidth doubling in an Ethernet passive optical network (EPON) enable an optical line terminal (OLT) to transmit downlink to at least one double rate optical network unit (ONU). The double rate transmission is preferably facilitated by use of single rate devices (OLT and ONU) functionally connected to provide the double rate capability. The methods include packet-by-packet multiplexing, bit-by-bit line code interleaving, doubling an inter-packet gap (IPG) length, defining windows of transmission for different transmission rates, using the 8B/10B code, removing the 8B/10B code from just the downlink transmission and symbol-by-symbol multiplexing is downlink transmissions from the double rate OLT.

4. 发明申请

WO2007132457A2 COMBINED DISTORTION ESTIMATION AND ERROR CORRECTION CODING FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的组合失真估计和错误校正编码
公开(公告)号：WO2007132457A2
公开(公告)日：2007-11-22
申请号：PCT/IL2007/000580
申请日：2007-05-10
申请人： ANOBIT TECHNOLOGIES LTD. , SHALVI, Ofir , SOMMER, Naftali , MAISLOS, Ariel , SOKOLOV, Dotan
发明人： SHALVI, Ofir , SOMMER, Naftali , MAISLOS, Ariel , SOKOLOV, Dotan
IPC分类号： G06F12/06
CPC分类号： G06F11/1072
摘要： A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.
摘要翻译：一种用于操作存储器件（24）的方法包括使用纠错码（ECC）对数据进行编码，并将编码数据作为第一模拟值存储在存储器件的相应模拟存储器单元（32）中。在存储编码数据之后，从其中存储有编码数据的存储器件的相应存储单元读取第二模拟值。至少一些第二模拟值与各自的第一模拟值不同。估计存在于第二模拟值中的失真。响应于估计的失真，相对于第二模拟值计算误差校正度量。使用ECC解码处理中的纠错度量来处理第二模拟值，以重构数据。

5. 发明申请

WO2007132453A3 DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES 审中-公开
公开(公告)号：WO2007132453A3
公开(公告)日：2007-11-22
申请号：PCT/IL2007/000576
申请日：2007-05-10
申请人： ANOBIT TECHNOLOGIES LTD. , SHALVI, Ofir , SOMMER, Naftali , GURGI, Eyal , MAISLOS, Ariel
发明人： SHALVI, Ofir , SOMMER, Naftali , GURGI, Eyal , MAISLOS, Ariel
IPC分类号： G11C29/00 , H03M13/00 , G11C16/04
摘要： A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

6. 发明申请

WO2003092207A1 FORWARD ERROR CORRECTION CODING IN ETHERNET NETWORKS 审中-公开
标题翻译：以太网网络中的前向纠错编码
公开(公告)号：WO2003092207A1
公开(公告)日：2003-11-06
申请号：PCT/IB2002/001370
申请日：2002-04-25
申请人： PASSAVE, INC. , KHERMOSH, Lior , MAISLOS, Ariel , HARAN, Onn
发明人： KHERMOSH, Lior , MAISLOS, Ariel , HARAN, Onn
IPC分类号： H04L1/00
CPC分类号： H04L1/0057 , H04L1/0084
摘要： A method for improving the bit error rate of Ethernet packets applies forward error correction (FEC) coding to transmitted packets. The FEC coding is systematic block coding, and is applied so that the coded packets can be interpreted by legacy network devices that are not capable of FEC decoding. The transmit and receive state machines of FEC-capable Ethernet nodes are modified to enable the nodes to encode and/or decode the packets with the FEC code, and to adapt the nodes' respective medium access layer (MAC) and physical layer (PHY) data rates.
摘要翻译：一种改善以太网分组比特误码率的方法对传输的分组进行前向纠错（FEC）编码。 FEC编码是系统块编码，并且被应用，使得编码分组可以由不能进行FEC解码的传统网络设备来解释。对具有FEC能力的以太网节点的发送和接收状态机进行修改，以使节点能够使用FEC码对分组进行编码和/或解码，并使节点各自的媒体接入层（MAC）和物理层（PHY）数据速率。

7. 发明申请

WO2006051519A2 DYNAMIC BANDWIDTH ALLOCATION PROCESSOR 审中-公开
标题翻译：动态带宽分配处理器
公开(公告)号：WO2006051519A2
公开(公告)日：2006-05-18
申请号：PCT/IL2005/000520
申请日：2005-05-19
申请人： PASSAVE LTD. , HARAN, Onn , MAISLOS, Ariel
发明人： HARAN, Onn , MAISLOS, Ariel
CPC分类号： H04W28/20 , H04L47/10 , H04W72/042
摘要： A dynamic bandwidth allocation (DBA) processor comprises a DBA co-processor having DBA co-processor components and operative to perform and accelerate DBA functions, and a processing core logically coupled to the DBA co-processor through a processing bus and operative to configure and dynamically control all the DBA co-processor components and to run sections of algorithms that cannot be accelerated on the DBA co-processor. The DBA processor significantly accelerated the bandwidth allocation in a communications network such as an optical communications network or a fast wireless network. The DBA co-processor and the processing core may be integrated on a chip.
摘要翻译：动态带宽分配（DBA）处理器包括具有DBA协处理器组件并且可操作以执行和加速DBA功能的DBA协处理器，以及通过处理总线逻辑耦合到DBA协处理器的处理核心，并且可操作地配置和动态控制所有DBA协处理器组件，并运行在DBA协处理器上无法加速的算法部分。 DBA处理器显着加速了通信网络（如光通信网络或快速无线网络）中的带宽分配。 DBA协处理器和处理核心可以集成在芯片上。

8. 发明申请

WO2004025903A2 METHODS FOR DYNAMIC BANDWIDTH ALLOCATION AND QUEUE MANAGEMENT IN ETHERNET PASSIVE OPTICAL NETWORKS 审中-公开
标题翻译：以太网无源光网络中动态带宽分配和队列管理的方法
公开(公告)号：WO2004025903A2
公开(公告)日：2004-03-25
申请号：PCT/IL2003/000702
申请日：2003-08-26
申请人： PASSAVE LTD. , HARAN, Onn , MAISLOS, Ariel , LIFSHITZ, Barak
发明人： HARAN, Onn , MAISLOS, Ariel , LIFSHITZ, Barak
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L47/13 , H04L47/2433 , H04L47/29 , H04L47/36 , H04Q11/0066 , H04Q11/0067 , H04Q11/0071 , H04Q2011/0064 , H04Q2011/0086 , H04Q2011/0088
摘要： In a passive optical network, dynamic bandwidth allocation and queue management methods and algorithms, desgiend to avoid fragmentation loss, guarantee that a length of a grant issued by an OLT will match precisely the count of bytes to be transmitted by an ONU. The methods include determining an ONU uplink transmission egress order based on a three-stage test, and various embodiments of methods for ONU report threshold setting.
摘要翻译：在无源光纤网络中，动态带宽分配和队列管理方法和算法，为了避免分段丢失而设计，保证由OLT发布的授权的长度将精确地匹配要被由ONU传输。该方法包括基于三阶段测试确定ONU上行链路传输出口顺序，以及用于ONU报告阈值设置的方法的各种实施例。

9. 发明申请

WO2004025394A2 OPERATIONS METHOD IN AN ETHERNET PASSIVE OPTICAL NETWORK THAT INCLUDES A NETWORK UNIT WITH MULTIPLE ENTITIES 审中-公开
标题翻译：以太网被动光网络中的操作方法，包括具有多个实体的网络单元
公开(公告)号：WO2004025394A2
公开(公告)日：2004-03-25
申请号：PCT/IL2003/000666
申请日：2003-08-11
申请人： PASSAVE LTD. , HARAN, Onn , MAISLOS, Ariel , KHERMOSH, Lior
发明人： HARAN, Onn , MAISLOS, Ariel , KHERMOSH, Lior
IPC分类号： G06F
CPC分类号： H04L45/00 , H04L47/13 , H04L47/2433 , H04L47/29 , H04L47/36 , H04Q11/0066 , H04Q11/0067 , H04Q11/0071 , H04Q2011/0064 , H04Q2011/0086 , H04Q2011/0088
摘要： A method for registration of multiple entities belonging to a specific optical networks unit (ONU). In one embodiment, the multiple entity registration method comprises checking by an optical line terminal (OLT) if a registration request message received from the specific ONU belongs to a certain grant, and based on the check result, registering an entity as either a first or as an additional entity of the specific ONU. In another embodiment, the method comprises checking by an OLT of a reserved value of a flags field inside a registration request message, and based on the check result, registering an entity as either a first or as an additional entity of the specific ONU. The knowledge by an OLT that multiple entities belong to a specific ONU is used for grant optimization and packet data flow optimization.
摘要翻译：一种用于注册属于特定光网络单元（ONU）的多个实体的方法。在一个实施例中，多实体注册方法包括：如果从特定ONU接收到的注册请求消息属于某一授权，则由光线路终端（OLT）进行检查，并且基于检查结果，将实体注册为第一或作为特定ONU的附加实体。在另一个实施例中，该方法包括由OLT检查注册请求消息内的标志字段的保留值，并且基于检查结果，将实体注册为特定ONU的第一个或附加实体。 OLT认识到多个实体属于特定的ONU，用于授权优化和分组数据流优化。

10. 发明申请

WO2014031799A1 HOST-ASSISTED COMPACTION OF MEMORY BLOCKS 审中-公开
标题翻译：主机协助记忆块的压缩
公开(公告)号：WO2014031799A1
公开(公告)日：2014-02-27
申请号：PCT/US2013/056069
申请日：2013-08-22
申请人： APPLE INC.
发明人： MAISLOS, Ariel , ROTBARD, Barak
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G06F2212/7208 , G06F2212/7209
摘要： In a system that includes a host and a memory controller that is separate from the host and stores data for the host in a non-volatile memory, a method for data storage includes transferring from the memory controller to the host one or more source blocks from the non-volatile memory for compaction. The source blocks are compacted in the host by copying valid data from the source blocks into one or more destination blocks. The destination blocks are transferred from the host to the memory controller, and the destination blocks are stored by the memory controller in the non-volatile memory.
摘要翻译：在包括与主机分离的主机和存储器控制器并且将主机的数据存储在非易失性存储器中的存储器控制器的系统中，用于数据存储的方法包括从存储器控制器向主机传送一个或多个源块用于压实的非易失性存储器。通过将源块中的有效数据复制到一个或多个目标块中，源块被压缩在主机中。目的地块从主机传送到存储器控制器，并且目的地块由存储器控制器存储在非易失性存储器中。

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