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1. 发明申请

WO1994022092A2 METHOD AND APPARATUS FOR IMPLEMENTING A COMMON MODE LEVEL SHIFT IN A BUS TRANSCEIVER INCORPORATING A HIGH SPEED BINARY DATA TRANSFER MODE WITH A TERNARY CONTROL TRANSFER MODE 审中-公开
标题翻译：用于实现具有三次控制传输模式的高速二进制数据传输模式的总线收发器中的公共模式电平转换的方法和装置
公开(公告)号：WO1994022092A2
公开(公告)日：1994-09-29
申请号：PCT/US1994002621
申请日：1994-03-11
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , OPRESCU, Florin , VAN BRUNT, Roger
IPC分类号： G06F13/40
CPC分类号： H04L25/028 , H04L5/16 , H04L25/0276 , H04L25/0292
摘要： The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. To permit the receivers of the present invention to receive the transmitted signals at the amplitude required to detect the proper bus voltage values, the present invention further provides a means for common mode shifting of the signals at the front end of the receivers while providing for a voltage offset independent of the fabrication process. This common mode shifting means also permits the implementation of a single ternary receiver in place of each of the binary, ternary and preemptive signaling receivers for each transceiver. In this manner, the present invention can be modified so that both transfer modes in addition to the preemptive signaling method can be performed using a single ternary receiver.
摘要翻译：本发明提供了一种总线收发器，其包括用于数据信号的半双工传输的具有用于控制信号的全双工传输的全双工主导逻辑传输方案的三进制控制传输模式的高速二进制传输模式。在本发明的一个实施例中，上述传送模式在总线架构中实现，总线架构包括经由双绞线串行总线耦合到第二通信节点的至少第一通信节点。每个节点包括第一收发器和第二收发器，其具有用于在总线信号状态上驱动的差分驱动器，该信号状态包括具有与符号相反的相等的电流幅度的第一和第二信号状态以及具有大约零电流幅度的第三信号状态，在数据传输阶段期间接收高速数据信号，以及在控制传输阶段期间接收控制信号的三元接收机。为了允许本发明的接收机以检测合适的总线电压值所需的振幅接收发送的信号，本发明还提供了一种用于在接收机前端对信号进行共模移位的装置，同时提供一个电压偏移与制造工艺无关。这种共模移动装置还允许实现单个三进制接收机来代替每个收发信机的二进制，三进制和抢先信令接收机中的每一个。以这种方式，可以修改本发明，使得可以使用单个三进制接收机来执行除抢先信令方法之外的两种传送模式。

2. 发明申请

WO1994022247A1 BUS TRANSCEIVER WITH BINARY DATA TRANSMISSION MODE AND TERNARY CONTROL TRANSMISSION MODE 审中-公开
标题翻译：具有二进制数据传输模式和三进制控制传输模式的总线收发器
公开(公告)号：WO1994022247A1
公开(公告)日：1994-09-29
申请号：PCT/US1994002670
申请日：1994-03-11
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , OPRESCU, Florin , VAN BRUNT, Roger
IPC分类号： H04L05/14
CPC分类号： H04L5/1423 , H04L12/4135
摘要： The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfert of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.
摘要翻译：本发明提供了一种总线收发器，其包括用于半双工传输数据信号的高速二进制传输模式，其具有用于全双工传输控制信号的全双工主导逻辑传输方案的三元控制传输模式。在本发明的一个实施例中，上述传送模式在总线架构中实现，总线架构包括经由双绞线串行总线耦合到第二通信节点的至少第一通信节点。每个节点包括第一收发器和第二收发器，其具有用于在总线信号状态上驱动的差分驱动器，该信号状态包括具有与符号相反的相等的电流幅度的第一和第二信号状态以及具有大约零电流幅度的第三信号状态，在数据传输阶段期间接收高速数据信号，以及在控制传送阶段接收控制信号的三元接收机。三进制接收机包括两个二进制接收器，用于在控制传输阶段期间由节点同时驱动控制信号期间检测在总线上产生的合成电流幅度，以及用于将总线上的合成电流幅度与本地驱动的信号状态组合的逻辑装置收发器，用于输出表示由相应收发器在总线上驱动的控制信号的重构控制信号。此外，两个收发器还包括用于检测抢占式控制消息的抢占式信令接收器，其用于在接收到该消息时终止数据传输阶段，从而可能发生更高优先级的控制传输。

3. 发明申请

WO1995027358A1 METHOD AND APPARATUS FOR IMPLEMENTING A COMMON MODE LEVEL SHIFT 审中-公开
标题翻译：实现共通模式电平转换的方法和装置
公开(公告)号：WO1995027358A1
公开(公告)日：1995-10-12
申请号：PCT/US1995003351
申请日：1995-03-22
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： H04L25/06
CPC分类号： H04L5/16 , H04L25/0276 , H04L25/028 , H04L25/0292 , H04L25/062
摘要： The level shifter provides a selective voltage level shift to a common mode signal level on a twisted pair signal line. The level shift is selectively performed based upon the input level of the common mode voltage. The level shifter is advantageously employed in a low voltage circuit wherein lacking sufficient voltage head room to accommodate a constant common mode level shift. An exemplary embodiment is described wherein the level shifter is employed within a bus transceiver of a bus system employing IEEE P1394 bus protocol. In the exemplary embodiment, the selective level shift is applied only to bus signals occurring during an idle phase and an arbitration phase, with no level shift performed during a data phase.
摘要翻译：电平移位器提供对双绞线信号线上的共模信号电平的选择性电压电平移位。基于共模电压的输入电平选择性地执行电平偏移。电平移位器有利地用在低电压电路中，其中缺少足够的电压头部空间以适应恒定的共模电平移位。描述了一种示例性实施例，其中电平移位器用于采用IEEE P1394总线协议的总线系统的总线收发器中。在示例性实施例中，选择性电平移位仅应用于在空闲阶段和仲裁阶段期间发生的总线信号，在数据阶段期间不执行电平漂移。

4. 发明申请

WO1994022220A1 DIFFERENTIAL- TO SINGLE-ENDED CMOS CONVERTER 审中-公开
标题翻译：差分到单端CMOS转换器
公开(公告)号：WO1994022220A1
公开(公告)日：1994-09-29
申请号：PCT/US1994002660
申请日：1994-03-11
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , VAN BRUNT, Roger
IPC分类号： H03K19/018
CPC分类号： H03K19/00384 , H03K19/018514
摘要： A differential-to-CMOS level signal converter which receives a first differential signal having a small amplitude difference between the binary signals. The differential-to-CMOS level converter amplifies and level shifts the binary differential signal and outputs a single-ended CMOS level signal suitable for use by digital CMOS logic. A circuit (E) for biasing the differential-to-CMOS level converter is coupled to the level shifting circuitry (C).
摘要翻译：差分至CMOS电平信号转换器，其接收二进制信号之间具有小振幅差的第一差分信号。差分至CMOS电平转换器对二进制差分信号进行放大和电平移位，并输出适合数字CMOS逻辑使用的单端CMOS电平信号。用于偏置差分至CMOS电平转换器的电路（E）耦合到电平转换电路（C）。

5. 发明申请

WO1994022093A2 METHOD AND APPARATUS FOR DYNAMIC, MULTI-SPEED BUS ARCHITECTURE WITH SPEED MESSAGES INDEPENDENT OF DATA SIGNAL TRANSFERS 审中-公开
标题翻译：用于动态，多速总线结构的方法和装置，具有独立于数据信号传输的速度信息
公开(公告)号：WO1994022093A2
公开(公告)日：1994-09-29
申请号：PCT/US1994002819
申请日：1994-03-11
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , OPRESCU, Florin , VAN BRUNT, Roger
IPC分类号： G06F13/42
CPC分类号： H04L12/40084 , G06F13/4072 , H04L5/20
摘要： A method for simultaneous transmission of signals on a bus having at least two nodes. The present invention provides a method and apparatus for driving a common node current on each of two lines of a twisted pair. The present invention also includes a method and apparatus for applying a voltage bias to each of the signal lines and then comparing the voltage bias with a first voltage derived from a second coupling of the first and second signal lines. The present invention also includes a method and means for generating a response signal corresponding to the voltage difference between the first voltage and the voltage bias.
摘要翻译：一种用于在具有至少两个节点的总线上同时传输信号的方法。本发明提供一种用于在双绞线的两条线路中的每条线上驱动公共节点电流的方法和装置。本发明还包括一种方法和装置，用于将电压偏压施加到每个信号线，然后将电压偏置与从第一和第二信号线的第二耦合导出的第一电压进行比较。本发明还包括用于产生对应于第一电压和电压偏压之间的电压差的响应信号的方法和装置。

6. 发明申请

WO1994020898A1 DE-SKEWER FOR SERIAL DATA BUS 审中-公开
标题翻译：串行数据总线的读取器
公开(公告)号：WO1994020898A1
公开(公告)日：1994-09-15
申请号：PCT/US1994002458
申请日：1994-03-09
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , OPRESCU, Florin , VAN BRUNT, Roger
IPC分类号： G06F01/10
CPC分类号： G06F1/10 , H04L7/0337 , H04L7/041 , H04L7/044
摘要： The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The deskewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.
摘要翻译：去串串利用延迟线来产生一组输入时钟信号的延迟版本。触发器组将延迟的时钟信号内的脉冲与设置在输入数据信号内的同步脉冲进行比较。检测器接收来自触发器的输出，并根据触发器的输出值选择具有最小偏移量的延迟时钟信号。多路复用器输出所选择的延迟时钟。该台式电脑提供了一种简单的开环电路，用于消除并行传输路径之间的偏差。去串串非常适合消除不随时间变化显着变化的源的偏移。特别地，解串器非常适用于提供高数据速率传输短脉冲串的数据传输系统。还描述了一种双刃式去串串，其能够产生用于消除占空比失真的一对时钟信号。

7. 发明申请

WO1994022248A1 DETERMINATION OF OPTIMAL CLOCK SIGNAL FOR SAMPLING A PACKET 审中-公开
标题翻译：确定用于采样包的最佳时钟信号
公开(公告)号：WO1994022248A1
公开(公告)日：1994-09-29
申请号：PCT/US1994002622
申请日：1994-03-11
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , VAN BRUNT, Roger , HILLMAN, Daniel, L. , NILSON, Christopher , OPRESCU, Florin , TEENER, Michael, D.
IPC分类号： H04L07/033
CPC分类号： H04L7/10 , H04L7/0066 , H04L7/0338 , H04L7/041
摘要： An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.
摘要翻译：一种用于检测数字信号的上升沿和下降沿的到达之间的系统差异并用于补偿差分的自适应数据分离器。来自发送源的数据分组以已知值的两个数据比特为前缀。数据分离器还提供每个位四个时钟信号，一个对应于理想上升沿，三个跟随每5纳秒。然后在每个时钟信号处对数据分组之前的两个前缀比特进行采样。由于给定数据分组中的所有信息经历相同的系统失真，所以自适应数据分离器的逻辑可以确定用于对数据包的每个数据位进行采样的最佳时钟信号。通过几个多路复用器，输入数据然后被计时到最佳时钟信号进行采样。

8. 发明申请

WO1994016507A1 DELAY LINE SEPARATOR FOR DATA BUS 审中-公开
标题翻译：数据总线延时线分离器
公开(公告)号：WO1994016507A1
公开(公告)日：1994-07-21
申请号：PCT/US1994000682
申请日：1994-01-12
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： H04L07/027
CPC分类号： H04L7/0066 , G06F13/423
摘要： The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.
摘要翻译：延迟线分离器从串行数据总线接收的组合数据/时钟编码信号中提取时钟信号，尽管存在显着的占空比失真。这种失真影响接收数据分组内符号的宽度，但不影响接收到的脉冲串内连续上升沿之间的时序。为了从失真信号中提取时钟信号，分离器利用一个预滤波器电路，其产生与接收信号中的每个上升沿同步的20纳秒脉冲。一个20纳秒脉冲串被传输到具有十二个延迟元件的延迟线上。电路连接到延迟线内的每隔一个延迟元件，以产生与脉冲序列的每个上升沿同步的10纳秒脉冲。来自电路的输出使用或门组合以产生10纳秒的时钟信号。预滤波器产生20纳秒脉冲而不是10纳秒脉冲，以确保脉冲成功地传播延迟线的整个长度，尽管在每个延迟元件内存在显着的色散。根据需要，将额外的电路抽入延迟元件，以产生延迟5或10纳秒间隔的附加时钟信号。

9. 发明申请

WO1994016390A1 METHOD AND APPARATUS FOR TRANSMITTING NRZ DATA SIGNALS ACROSS AN ISOLATION BARRIER DISPOSED IN AN INTERFACE BETWEEN ADJACENT DEVICES ON A BUS 审中-公开
标题翻译：用于通过在总线上的相邻设备之间的接口中处理的隔离障碍物发送NRZ数据信号的方法和装置
公开(公告)号：WO1994016390A1
公开(公告)日：1994-07-21
申请号：PCT/US1993012324
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , H03M5/18 , H04L25/0266 , H04L25/4925
摘要： The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has as a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus accross the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a hight transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving as input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.
摘要翻译：本发明提供了一种用于在跨越经由总线相互连接的两个设备之间的隔离屏障的接口上传输NRZ数据信号的方法和装置。该装置包括用于接收NRZ数据信号并输出微分信号的信号微分器。包括三态门的驱动器具有数据信号的第一输入端和作为第二输入端的微分信号，用于当微分信号为高电平时使能三态门。偏置电压被施加到三态门的输出端以导出作为输出的传输信号，用于经由总线通过两个设备之间的接口进行传输。以这种方式，当三态门禁用时，从第一装置输出的传输信号包括对应于偏置电压的中间传输信号，当三态门被使能时的高传输信号，以及第三输入到三态门并且当三态门被使能且第一输入到三态门时，低传输信号为低。提供施密特触发器作为第二设备中的接收器，用于作为输入接收传输信号并输出对应于同步数据信号的重建数据信号。

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