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1. 发明申请

WO1997041665A1 D.T.R.M. DATA TIMING RECOVERY MODULE 审中-公开
标题翻译： D.T.R.M. 数据时序恢复模块
公开(公告)号：WO1997041665A1
公开(公告)日：1997-11-06
申请号：PCT/SE1997000665
申请日：1997-04-18
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , MOZETIC, Carlo , TESTA, Francesco
发明人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
IPC分类号： H04L07/033
CPC分类号： H04L7/033 , H03B5/1203 , H03B5/1231 , H03B5/1256 , H03L7/24 , H04L7/0083 , H04L7/027
摘要： A data timing recovery system for clock recovery based on a pulse generator circuit (106) and an injection locked oscillator (306) ILO, which extracts the clock signal at high rate and preserves the timing information during long "0" or "1" sequences. This system may also include a clock extractor circuit (102) including the ILO, a phase aligner circuit (104) and a clock killer circuit (108). Connections to and from the system are an incoming data link (110), an outgoing data link (122), an outgoing clock link (120), an enable/disable link (114) and a loss of signal data link (156). A data link (112) connected between the pulse generator circuit and the phase aligner circuit and to the clock killer circuit. A pulse link (116) connected to the ILO. A recovered clock link (118) connected between the clock extractor circuit and the phase aligner circuit.
摘要翻译：一种用于基于脉冲发生器电路（106）和注入锁定振荡器（306）ILO的时钟恢复的数据定时恢复系统，其以高速率提取时钟信号并在长“0”或“1”序列期间保留定时信息。该系统还可以包括包括ILO的时钟提取器电路（102），相位对准器电路（104）和时钟抑制电路（108）。与系统的连接是输入数据链路（110），输出数据链路（122），输出时钟链路（120），使能/禁止链路（114）和信号数据链路丢失（156）。连接在脉冲发生器电路和相位对准器电路和时钟抑制电路之间的数据链路（112）。连接到国际劳工组织的脉冲链路（116）。连接在时钟提取电路和相位对准器电路之间的恢复时钟链路（118）。

2. 发明申请

WO1991019371A1 METHOD AND APPARATUS FOR TIMING RECOVERY IN DIGITAL DATA COMMUNICATIONS SYSTEMS 审中-公开
标题翻译：用于数字数据通信系统中时序恢复的方法和装置
公开(公告)号：WO1991019371A1
公开(公告)日：1991-12-12
申请号：PCT/CA1991000172
申请日：1991-05-23
申请人： NORTHERN TELECOM LIMITED
发明人： NORTHERN TELECOM LIMITED , CAPKUN, Edward, Anthony , ARNON, Ephraim
IPC分类号： H04L07/033
CPC分类号： H04L7/0334 , H04L7/0337 , H04L7/044
摘要： In apparatus for receiving digital data signals in a digital communication system, especially an Integrated Services Digital Network, timing recovery problems associated with erratic zero crossing when multiple terminals transmit to a common receiver are mitigated by detecting the rate of change of the digital data signal between two predetermined positions (C1, C2) and controlling sampling of the digital data signal in dependence upon the difference between such rate of change and a reference. The rate of change conveniently corresponds to the trailing ''corner'' of a framing pulse (F), i.e. the point at which the signal commences the transition from one polarity to the other. The ''corner'' is much more stable, i.e. less susceptible to variation due to multiple terminal effects, than the zero-crossing which follows it, since the zero crossing may vary relative to the ''corner''. The transition may be determined by sampling the digital data signal at two discrete positions and determining when the two resulting samples differ in amplitude by a predetermined amount. One of the two pulses (C1, C2), namely the one with the larger amplitude (1), may then be used for data recovery.

3. 发明申请

WO1991007832A1 METHOD AND APPARATUS FOR CLOCK RECOVERY IN DIGITAL COMMUNICATION SYSTEMS 审中-公开
标题翻译：数字通信系统中时钟恢复的方法与装置
公开(公告)号：WO1991007832A1
公开(公告)日：1991-05-30
申请号：PCT/US1990006638
申请日：1990-11-13
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： DIGITAL EQUIPMENT CORPORATION , PEARSON, Jonathan, D.
IPC分类号： H04L07/033
CPC分类号： H04L7/033 , H04L7/027
摘要： A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ('PLL'), preferably employing a Sequential Phase/Frequency Detector to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL.

4. 发明申请

WO1991005422A1 PHASE DETECTOR FOR PHASE-LOCKED LOOP CLOCK RECOVERY SYSTEM 审中-公开
标题翻译：相锁定循环时钟恢复系统的相位检测器
公开(公告)号：WO1991005422A1
公开(公告)日：1991-04-18
申请号：PCT/US1990005579
申请日：1990-10-01
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , DEVITO, Lawrence, M.
IPC分类号： H04L07/033
CPC分类号： H04L7/033 , H03L7/091
摘要： A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes four latches, serially interconnected, with the first latch (70) receiving the information signal and each subsequent latch receiving the data outpout of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) (20) gate receives a delayed information signal and the data output of the second latch (72). A second XOR gate (22) receives the data output of the second latch (72) and the data output of the third latch (74). A third XOR (24) gate receives the data output of the third latch (74) and the data output of the fourth latch (76). A control element, responsive to the outputs of the first, second, third XOR gates, controls the voltage across a capacitor, which has at least one electrode serving as an output terminal for producing the phase error signal. The phase-locked loop clock recovery system provides zero static phase offset and minimal phase jitter in response to data density variations in the information signal.

5. 发明申请

WO1997044930A1 FREQUENCY GENERATING CIRCUIT 审中-公开
标题翻译：频率发生电路
公开(公告)号：WO1997044930A1
公开(公告)日：1997-11-27
申请号：PCT/IB1997000327
申请日：1997-04-01
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , MARSTON, Paul, Stewart , VAN VELDHUIZEN, Evert, D.
IPC分类号： H04L07/033
CPC分类号： H04L7/0331
摘要： A receiving apparatus has a clock frequency generating circuit comprising in a first embodiment a low cost oscillator whose frequency is higher than the wanted clock frequency and in a second embodiment a low cost oscillator whose frequency can be higher or lower than the wanted clock frequency. By means of subtracting pulses from (first embodiment) or adding/subtracting pulses (second embodiment) to/from the output of the low cost oscillator, a clock frequency is generated which is stable within a specified tolerance range. More particularly, the receiving apparatus comprises means (10, 12) for receiving a transmitted signal, means (14, 16) for deriving a repetitive reference signal from the received transmitted signal, clock signal generating means (22, 24, 32) for generating a clock signal having a frequency corresponding substantially to a desired frequency, and means (36, 42, 46) for determining whether the clock frequency generated in respective time periods between successive reference signals varies relative to an arbitrarily set value, said means providing a control signal which is used to adjust the frequency of the generated clock signal.
摘要翻译：接收装置具有时钟频率产生电路，其在第一实施例中包括频率高于有用时钟频率的低成本振荡器，在第二实施例中包括频率可以高于或低于所需时钟频率的低成本振荡器。通过从低成本振荡器的输出中减去（第一实施例）的脉冲或加/减脉冲（第二实施例），产生在规定的公差范围内稳定的时钟频率。更具体地，接收装置包括用于接收发送信号的装置（10,12），用于从接收到的发送信号中导出重复参考信号的装置（14,16），用于产生用于产生信号的时钟信号产生装置（22,24,32）具有基本上对应于期望频率的频率的时钟信号，以及用于确定在连续参考信号之间的各个时间段中产生的时钟频率是否相对于任意设置的值变化的装置（36,42,46），所述装置提供控制信号用于调整产生的时钟信号的频率。

6. 发明申请

WO1996005672A1 INTEGRABLE CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：积时钟恢复电路
公开(公告)号：WO1996005672A1
公开(公告)日：1996-02-22
申请号：PCT/DE1995001038
申请日：1995-08-08
申请人： SIEMENS AKTIENGESELLSCHAFT , TRUMPP, Gerhard
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H04L07/033
CPC分类号： G06F1/04 , H03L7/07 , H03L7/0812 , H04L7/005 , H04L7/0083 , H04L7/0091 , H04L7/0337
摘要： A process and a fully integrable clock circuit are proposed for recovering a clock signal from a data stream. A locally available reference clock signal, preferably one of two complementary reference clock signals, is fed into each of two groups of phase regulators in each of which one phase regulator which has assumed a state within its operational range is selected for the preparation of the recovered clock signal, while a non-selected phase regulator is kept in readiness in a state within its operational range and diametrically opposite to that of the selected phase regulator. Once the limit of the operational range of the selected phase regulator is reached, a switch-over to the phase regulator which has been kept in readiness takes place.
摘要翻译：它提出了一种方法和用于回收从数据流中的时钟信号的完全集成的电路布置。两组移相器是本地可用的参考时钟信号，优选地，每个供给彼此互补的参考时钟信号中的一个。分别，已经假定其工作范围内的状态的相位调节器，则选择当前未选择的相位调节器中，以提供恢复的时钟信号在其操作范围内保持准备在直径状态到当前选定的相位调节器的状态。当到达当前选择的相位校正器的工作区域的边界被切换到之前保持的准备阶段控制器。

7. 发明申请

WO1993012601A1 TIMING AND AUTOMATIC FREQUENCY CONTROL OF DIGITAL RECEIVER USING THE CYCLIC PROPERTIES OF A NON-LINEAR OPERATION 审中-公开
标题翻译：使用非线性运算的循环特性对数字接收机的时序和自动频率控制
公开(公告)号：WO1993012601A1
公开(公告)日：1993-06-24
申请号：PCT/CA1992000536
申请日：1992-12-08
申请人： NOVATEL COMMUNICATIONS, LTD.
发明人： NOVATEL COMMUNICATIONS, LTD. , SCOTT, Kenneth, E. , KAUBE, Michael , ANVARI, Kiomars
IPC分类号： H04L07/033
CPC分类号： H04L7/0054 , H04L27/2332 , H04L2027/003 , H04L2027/0055
摘要： A technique for correcting the sampling time and carrier frequency error in a receiver for digitally modulated signals. Discrete-time, complex-valued samples of the incoming signal are fed to a pair of non-linear operators such as correlators. The first correlator provides a signal having a first phase component related to the symbol timing error and a second phase component related to the carrier frequency error. The second correlator provides a signal having a first phase component related to the symbol timing error and a second phase component related to the negative of the carrier frequency error. The phase components are then separated and detected to extract an estimate of the symbol timing error and the carrier frequency error. In the preferred embodiment, the complex-valued samples are frequency-shifted, before being fed to the correlators, so that the phase components of interest appear at zero frequency. The invention satisfactorily demodulates transmitted digital signals in applications, such as cellular time-division multiple access (TDMA), where they are susceptible to multipath fading.

8. 发明申请

WO1992019056A1 METHOD FOR SYNCRHONISING INPUT DATA OF A COMPUTING PROCESSOR AND DEVICE FOR IMPLEMENTING SUCH METHOD 审中-公开
标题翻译：用于同步计算处理器的输入数据的方法和用于实现这种方法的装置
公开(公告)号：WO1992019056A1
公开(公告)日：1992-10-29
申请号：PCT/FR1992000356
申请日：1992-04-21
申请人： THOMSON-CSF
发明人： THOMSON-CSF , DEMEURE, Alain , RICHARD, Eric , CLEMENT, Jean-Pierre
IPC分类号： H04L07/033
CPC分类号： H04L7/0338 , G06F13/4256
摘要： The present invention relates to a method for the synchronization of input data of a computing processor consisting in generating from a central clock a plurality of local clocks which are out of phase with respect to each other, sampling the input data with each of said local clocks and selecting the sampled signal presenting rising fronts positioned temporarily in the middle of stable states. The invention also relates to a device for implementing such method. Application: parallel computers.

9. 发明申请

WO1991003895A1 CLOCK RECOVERY APPARATUS 审中-公开
标题翻译：时钟恢复装置
公开(公告)号：WO1991003895A1
公开(公告)日：1991-03-21
申请号：PCT/US1990004827
申请日：1990-08-24
申请人： RAYNET CORPORATION
发明人： RAYNET CORPORATION , APPLE, William, Ray , FREEMAN, William, R. , SODERBERG, Paulmer , THOMPSON, Lyle , THOMAS, Mark, Stephen
IPC分类号： H04L07/033
CPC分类号： H04L7/0338
摘要： A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.
摘要翻译：数字相位获取电路包括用于检测输入数据和多个候选时钟相位的边缘的逻辑，该电路还包括用于确定数据何时经历相变的逻辑和经历数字等效转换的至少一个候选相位时间到数据转换，以使候选阶段能够用于恢复表示数据的信息的时钟。电路允许在发生预定数据转换的1位时间内恢复时钟，从而允许在数据分组中使用1比特的前导码。

10. 发明申请

WO1990007238A1 METASTABLE-FREE DIGITAL SYNCHRONIZER WITH LOW PHASE ERROR 审中-公开
标题翻译：具有低相位误差的无数字数字同步器
公开(公告)号：WO1990007238A1
公开(公告)日：1990-06-28
申请号：PCT/US1989005787
申请日：1989-12-15
申请人： DATAPOINT CORPORATION
发明人： DATAPOINT CORPORATION , FISCHER, Michael, A. , COX, William, M.
IPC分类号： H04L07/033
CPC分类号： H04L7/0338 , H04L25/03006 , H04L25/4919
摘要： An output clock signal (28) is synchronized with predetermined phase accuracy relative to an internal stable frequency reference clock signal (22) upon the application of a transition of an asynchronous event signal (24). A plurality of phase shifted versions of the reference clock signal (22) are derived. Upon the occurrence of the asynchronous signal (24), the states of the phase shifted versions are sampled, and that information is utilized as a code to select one of the phase shifted versions from which the output clock signal (28) is derived. Synchronization occurs rapidly within the metastable settling time of the flip flops of a register (96) which sample or decode the states of the phase shifted versions, or by logical gating arrangements which avoid the necessity for considering the metastable signal. Synchronization is typically obtainable in less than the period of one reference clock signal.
摘要翻译：在施加异步事件信号（24）的转换时，输出时钟信号（28）相对于内部稳定频率参考时钟信号（22）与预定的相位精度同步。导出参考时钟信号（22）的多个相移版本。在发生异步信号（24）时，对相移版本的状态进行采样，并且将该信息用作代码以选择推导出输出时钟信号（28）的相移版本中的一个。在对采样或解码相移版本的状态的寄存器（96）的触发器的亚稳定建立时间内，或通过避免考虑亚稳态信号的必要性的逻辑选通布置，快速发生同步。通常可以在一个参考时钟信号的周期内获得同步。

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