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1. 发明申请

WO2004073047A3 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存存储器件在紫外线诱发充电中的紫外线阻挡层
公开(公告)号：WO2004073047A3
公开(公告)日：2004-10-07
申请号：PCT/US2004000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES INC , NGO MINH VAN , KAMAL TAZRIEN , RAMSBEY MARK T , HALLIYAL ARVIND , PARK JAEYONG , CHENG NING , ERHARDT JEFF P , SHIELDS JEFFREY A , FERGUSON CLARENCE , HUI ANGELA T , HUERTAS ROBERT A , GOTTIPATI TYAGAMOHAN
发明人： NGO MINH VAN , KAMAL TAZRIEN , RAMSBEY MARK T , HALLIYAL ARVIND , PARK JAEYONG , CHENG NING , ERHARDT JEFF P , SHIELDS JEFFREY A , FERGUSON CLARENCE , HUI ANGELA T , HUERTAS ROBERT A , GOTTIPATI TYAGAMOHAN
IPC分类号： H01L21/28 , H01L21/336 , H01L23/552 , H01L27/115 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS闪存单元（24）免受UV感应充电的方法，包括在半导体器件（10,50）中制造SONOS闪存单元（24）; 以及在所述SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上不透紫外线的材料。一种包括SONOS闪速存储器单元（24）的SONOS闪速存储器件（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上不透紫外线的材料。

2. 发明申请

WO2005010984A3 PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING IN AN EEPROM 审中-公开
标题翻译： PECVD硅氧化物层，用于在EEPROM中减少紫外线充电
公开(公告)号：WO2005010984A3
公开(公告)日：2005-03-24
申请号：PCT/US2004019664
申请日：2004-06-18
申请人： ADVANCED MICRO DEVICES INC , NGO MINH VAN , RAMSBEY MARK T , KAMAL TAZRIEN , GAO PEI YUAN
发明人： NGO MINH VAN , RAMSBEY MARK T , KAMAL TAZRIEN , GAO PEI YUAN
IPC分类号： H01L21/316 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/552 , H01L27/115 , H01L21/314
CPC分类号： H01L27/11521 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer (500) having reduced UV transmission is deposited by PECVD, on an interlayer dielectric (300) , prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer (500) having a refractive index (R.I.) of 1.7 to 2.0. The Si-rich silicon oxide layer (SiRo) reduces UV cell charging problems in the fabrication of EEPROM flash memories.
摘要翻译：在金属化之前，通过PECVD在层间电介质（300）上沉积具有减少的UV透射的富Si氧化硅层（500），从而减小Vt。实施例包括沉积不透紫外线的富Si氧化硅层（500）折射率（RI）为1.7〜2.0。富Si硅氧化物层（SiRo）减少了制造EEPROM闪速存储器中的UV电池充电问题。

3. 发明申请

WO2004079824A3 CHARGE-TRAPPING MEMORY ARRAYS 审中-公开
标题翻译：充电跟踪记忆阵列
公开(公告)号：WO2004079824A3
公开(公告)日：2004-10-28
申请号：PCT/US2004000502
申请日：2004-01-08
申请人： SPANSION LLC , KAMAL TAZRIEN , RAMSBEY MARK T , SHIRAIWA HIDEHIKO , CHEUNG FRED TK
发明人： KAMAL TAZRIEN , RAMSBEY MARK T , SHIRAIWA HIDEHIKO , CHEUNG FRED TK
IPC分类号： H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115 , H01L2224/48247 , H01L2224/85464 , H01L2924/01012 , H01L2924/01019 , H01L2924/01021 , H01L2924/01057 , H01L2924/01087 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , Y10S257/90 , H01L2924/00
摘要： The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordlines (201) adjacent to the bitline contacts (240) to prevent damage caused during the formation of the bitline contacts (240). The present invention also relates to a method of forming the memory array.
摘要翻译：本发明涉及一种存储器阵列（100），其包括具有触点（240）和与所述位线（224）相交的多个字线（201,202）的基板（222）和多个位线（224）。保护间隔物（234）用于将位线触点（240）与位线接触件（240）相邻的字线（201）分开，以防止在形成位线触头（240）期间造成的损坏。本发明还涉及形成存储器阵列的方法。

4. 发明申请

WO03001601A3 SPACER ETCH MASK FOR SONOS MEMORY 审中-公开
标题翻译：用于SONOS存储器的间隔蚀刻掩模
公开(公告)号：WO03001601A3
公开(公告)日：2003-03-13
申请号：PCT/US0148825
申请日：2001-12-14
申请人： ADVANCED MICRO DEVICES INC
发明人： RAMSBEY MARK T , DERHACOBIAN NARBEH , WANG JANET , HUI ANGELA , PHAM TUAN , SUNKAVALLI RAVI , RANDOLPH MARK
IPC分类号： H01L21/8246 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers (56) in a SONOS type nonvolatile semiconductor memory device, involving providing a substrate (40) having a core region (42) and periphery region (44), the core region (42) containing SONOS type memory cells (48) and the periphery region (44) containing gate transistors (50); implanting a first implant into the core region (42) and a first implant into the perifery region (44) of the substrate (40); forming a spacer material (52) over the substrate (40); masking the core region (42) and forming spacers (56) adjacent the gate transistors (50) in the perifery region (44); and implanting a second implant into the perifery region (44) of the substrate (40).
摘要翻译：本发明的一个方面涉及一种在SONOS型非易失性半导体存储器件中形成间隔物（56）的方法，包括提供具有芯区（42）和周边区（44）的基底（40），芯区（ 42），包含SONOS型存储单元（48）和包含栅极晶体管（50）的外围区域（44）; 将第一植入物植入所述芯区域（42）中并将第一植入物植入所述基底（40）的所述外围区域（44）中; 在衬底（40）上形成间隔物（52）; 掩蔽所述芯区域（42）并在所述外形区域（44）中形成与所述栅极晶体管（50）相邻的间隔物（56）。以及将第二植入物植入到所述基底（40）的外围区域（44）中。

5. 发明申请

WO03032393A3 DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY 审中-公开
标题翻译： SONOS闪存中的双密封核心门
公开(公告)号：WO03032393A3
公开(公告)日：2003-10-09
申请号：PCT/US0231330
申请日：2002-09-30
申请人： ADVANCED MICRO DEVICES INC
发明人： SUN YU , VAN BUSKIRK MICHAEL A , RAMSBEY MARK T
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118) around the first set of memory cell gates (116); and forming a second set of memory cell gates (122) in the core region, wherein each memory cell gate of the second set of memory cell gates (122) is adjacent to at least one memory cell gate of the first set of memory cell gates (116), each memory cell gate of the first set of memory cell gates (116) is adjacent at least one memory cell gate of the second set of memory cell gates (122), and the conformal insulation material layer (118) is positioned between each adjacent memory cell gate is disclosed.
摘要翻译：一种形成非易失性半导体存储器件的方法，包括在衬底（112）上形成电荷捕获电介质（114）; 在芯区域中的电荷捕获电介质（114）上形成第一组存储器单元栅极（116）; 在第一组存储单元栅极（116）周围形成保形绝缘材料层（118）; 以及在所述核心区域中形成第二组存储单元门（122），其中所述第二组存储单元门（122）的每个存储单元门与所述第一组存储单元门的至少一个存储单元门相邻（116），所述第一组存储单元门（116）的每个存储单元栅极与所述第二组存储单元门（122）的至少一个存储单元栅极相邻，并且所述保形绝缘材料层（118）被定位在每个相邻的存储单元门之间公开。

6. 发明申请

WO03030253A3 SALICIDED GATE FOR VIRTUAL GROUND ARRAYS 审中-公开
标题翻译：用于虚拟接地阵列的杀手门
公开(公告)号：WO03030253A3
公开(公告)日：2003-08-28
申请号：PCT/US0230784
申请日：2002-09-27
申请人： ADVANCED MICRO DEVICES INC
发明人： RAMSBEY MARK T , SUN YU , CHANG CHI
IPC分类号： H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11531
摘要： Processes for doping and saliciding word lines (20) in a virtual ground array flash memory device without causing shorting between bit lines (26) are disclosed. According to one aspect, word lines (20) are doped prior to patterning the poly layer from which the word lines (20) are formed in the core region. Thereby, the poly layer protects the substrate between the word lines (20) from doping that could cause shorting between bit lines (26). According to another aspect, word lines (20) are exposed while spacer material, dielectric, or like material protects the substrate between word lines (20). The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines (26). Disclosed are virtual ground array flash memory devices with doped and salicided word lines (20), but no shorting between bit lines (26) even in virtual ground arrays where there are no oxide island isolation regions (28) between bit lines (26).
摘要翻译：公开了在虚拟接地阵列闪存器件中掺杂和助化字线（20）而不引起位线（26）之间短路的过程。根据一个方面，在图案化在核心区域中形成字线（20）的多晶层之前，掺杂字线（20）。从而，多晶硅层保护字线（20）之间的衬底免受可能导致位线（26）之间短路的掺杂。根据另一方面，字线（20）被暴露，而间隔材料，电介质或类似材料保护字线（20）之间的衬底。间隔物材料或电介质以类似于掺杂的方式防止衬底变成硅化物，从而可能导致位线（26）之间短路。公开了具有掺杂和硅化字线（20）的虚拟接地阵列闪存器件，但即使在位线（26）之间不存在氧化物岛隔离区域（28）的虚拟接地阵列中，位线（26）之间也不短路。

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