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1. 发明申请

WO2005045935A3 SIDEWALL FORMATION FOR HIGH DENSITY POLYMER MEMORY ELEMENT ARRAY 审中-公开
标题翻译：高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：WO2005045935A3
公开(公告)日：2005-10-13
申请号：PCT/US2004031275
申请日：2004-09-23
申请人： ADVANCED MICRO DEVICES INC , LYONS CHRISTOPHER F , CHANG MARK S , LOPATIN SERGEY D , SUBRAMANIAN RAMKUMAR , CHEUNG PATRICK , NGO MINH VAN , OGLESBY JANE V
发明人： LYONS CHRISTOPHER F , CHANG MARK S , LOPATIN SERGEY D , SUBRAMANIAN RAMKUMAR , CHEUNG PATRICK , NGO MINH VAN , OGLESBY JANE V
IPC分类号： G11C11/56 , G11C13/02 , H01L27/115 , H01L27/28 , H01L29/68 , H01L45/00 , H01L51/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells (115) can have a bit line (610) of the wafer (806) as the first electrode (104, 1502) and operate with a second formed electrode (110, 1504) to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储器单元的数量的系统和方法。该系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的存储元件。侧壁存储器单元（115）可以具有作为第一电极（104,1502）的晶片（806）的位线（610）并且与第二形成的电极（110,1504）一起操作以激活一部分有机在它们之间形成的问题。

2. 发明申请

WO2005045935A2 SIDEWALL FORMATION FOR HIGH DENSITY POLYMER MEMORY ELEMENT ARRAY 审中-公开
标题翻译：高密度聚合物存储元件阵列的形成
公开(公告)号：WO2005045935A2
公开(公告)日：2005-05-19
申请号：PCT/US2004/031275
申请日：2004-09-23
申请人： ADVANCED MICRO DEVICES, INC. , LYONS, Christopher, F. , CHANG, Mark, S. , LOPATIN, Sergey, D. , SUBRAMANIAN, Ramkumar , CHEUNG, Patrick , NGO, Minh, Van , OGLESBY, Jane, V.
发明人： LYONS, Christopher, F. , CHANG, Mark, S. , LOPATIN, Sergey, D. , SUBRAMANIAN, Ramkumar , CHEUNG, Patrick , NGO, Minh, Van , OGLESBY, Jane, V.
IPC分类号： H01L27/115
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells (115) can have a bit line (610) of the wafer (806) as the first electrode (104, 1502) and operate with a second formed electrode (110, 1504) to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元（115）可以具有作为第一电极（104,1502）的晶片（806）的位线（610）并且与第二形成的电极（110,1504）一起操作以激活有机物的一部分之间形成的事物。

3. 发明申请

WO2005010984A3 PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING IN AN EEPROM 审中-公开
标题翻译： PECVD硅氧化物层，用于在EEPROM中减少紫外线充电
公开(公告)号：WO2005010984A3
公开(公告)日：2005-03-24
申请号：PCT/US2004019664
申请日：2004-06-18
申请人： ADVANCED MICRO DEVICES INC , NGO MINH VAN , RAMSBEY MARK T , KAMAL TAZRIEN , GAO PEI YUAN
发明人： NGO MINH VAN , RAMSBEY MARK T , KAMAL TAZRIEN , GAO PEI YUAN
IPC分类号： H01L21/316 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/552 , H01L27/115 , H01L21/314
CPC分类号： H01L27/11521 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer (500) having reduced UV transmission is deposited by PECVD, on an interlayer dielectric (300) , prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer (500) having a refractive index (R.I.) of 1.7 to 2.0. The Si-rich silicon oxide layer (SiRo) reduces UV cell charging problems in the fabrication of EEPROM flash memories.
摘要翻译：在金属化之前，通过PECVD在层间电介质（300）上沉积具有减少的UV透射的富Si氧化硅层（500），从而减小Vt。实施例包括沉积不透紫外线的富Si氧化硅层（500）折射率（RI）为1.7〜2.0。富Si硅氧化物层（SiRo）减少了制造EEPROM闪速存储器中的UV电池充电问题。

4. 发明申请

WO2004084299A3 SHALLOW TRENCH ISOLATION IN PROCESSES WITH STRAINED SILICON 审中-公开
公开(公告)号：WO2004084299A3
公开(公告)日：2004-09-30
申请号：PCT/US2004/007464
申请日：2004-03-11
申请人： ADVANCED MICRO DEVICES, INC. , WANG, Haihong , NGO, Minh, Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
发明人： WANG, Haihong , NGO, Minh, Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
IPC分类号： H01L21/762
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

5. 发明申请

WO2004073047A2 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存器件在BEOL加工中紫外线诱导充电的紫外线阻挡层
公开(公告)号：WO2004073047A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
发明人： NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
IPC分类号： H01L
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS快闪存储单元（24）不受紫外线感应充电的方法，包括在半导体器件（10,50）中制造SONOS快闪存储单元（24）; 以及在SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上UV不透明材料。包括SONOS闪存单元（24）的SONOS闪存设备（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上UV不透明材料。

6. 发明申请

WO2004066368A2 SHALLOW TRENCH ISOLATION PROCESS FOR STRAINED SILICON PROCESSES 审中-公开
标题翻译：用于应变硅工艺的浅层分离工艺
公开(公告)号：WO2004066368A2
公开(公告)日：2004-08-05
申请号：PCT/US2004/000982
申请日：2004-01-13
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh-Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
发明人： NGO, Minh-Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
IPC分类号： H01L
CPC分类号： H01L21/76224
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can form the liner.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。低温过程可以是LPCVD。退火步骤可以形成衬套。

7. 发明申请

WO2003046971A1 METHOD FOR FORMING AN OXYNITRIDE SPACER FOR A METAL GATE ELECTRODE USING A PECVD PROCESS WITH A SILICON-STARVING ATMOSPHERE 审中-公开
标题翻译：使用具有硅取代大气的PECVD工艺形成金属栅极电极的氧化物间隔物的方法
公开(公告)号：WO2003046971A1
公开(公告)日：2003-06-05
申请号：PCT/US2002/032582
申请日：2002-10-11
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , HALLIYAL, Arvind
发明人： NGO, Minh, Van , HALLIYAL, Arvind
IPC分类号： H01L21/318
CPC分类号： H01L21/3145 , C23C16/308 , H01L21/28079 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (100) and a method of making the semiconductor device (100) including a metal gate electrode (110), including a semiconductor substrate (102); a metal gate electrode (110); and a silicon oxynitride spacer (114) formed on a surface of the metal gate electrode (110), wherein an interface of the silicon oxynitride spacer (114) and the metal gate electrode (110) is substantially free of metal silicide. The process includes steps of forming a metal gate electrode on a semiconductor substrate; forming by PECVD on a surface of the metal gate electrode a silicon oxynitride spacer, wherein the silicon oxynitride spacer is formed under initially silicon-starved conditions in which a first quantity of at least one silicon-containing material is provided to a PECVD apparatus which is reduced relative to an amount of at least one other reactant, as a result of which substantially no silicide is formed.
摘要翻译：一种半导体器件（100）以及包括半导体衬底（102）的包括金属栅电极（110）的半导体器件（100）的制造方法。金属栅电极（110）; 以及形成在所述金属栅极（110）的表面上的氮氧化硅间隔物（114），其中所述氧氮化硅间隔物（114）和所述金属栅电极（110）的界面基本上不含金属硅化物。该方法包括在半导体衬底上形成金属栅电极的步骤; 通过PECVD在金属栅电极的表面上形成氮氧化硅间隔物，其中在最初的硅饥饿条件下形成氮氧化硅间隔物，其中第一量的至少一种含硅材料被提供给PECVD装置，该PECVD装置是相对于至少一种其它反应物的量减少，结果基本上没有形成硅化物。

8. 发明申请

WO2007050270A2 SYSTEM AND METHOD FOR PROCESSING AN ORGANIC MEMORY CELL 审中-公开
标题翻译：用于处理有机存储器单元的系统和方法
公开(公告)号：WO2007050270A2
公开(公告)日：2007-05-03
申请号：PCT/US2006/039398
申请日：2006-10-06
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , SOKOLIK, Igor , KINGBOROUGH, Richard, P. , LEONARD, William, G. , YUDANOV, Nicolay, F. , PANGRLE, Suzette, K. , TRIPSAS, Nicholas, H. , NGO, Minh, Van
发明人： SOKOLIK, Igor , KINGBOROUGH, Richard, P. , LEONARD, William, G. , YUDANOV, Nicolay, F. , PANGRLE, Suzette, K. , TRIPSAS, Nicholas, H. , NGO, Minh, Van
IPC分类号： C23C14/12
CPC分类号： H01L51/001 , C23C16/54 , H01J2237/3321 , H01L27/285
摘要： A system (200) and method are disclosed for processing an organic memory cell. An exemplary system (200) can employ an enclosed processing chamber (202), a passive layer formation component (204) operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component (206) operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system (200) can further employ a second electrode formation component (208) operative to form a second electrode on the organic semiconductor layer.
摘要翻译：公开了一种用于处理有机存储器单元的系统（200）和方法。示例性系统（200）可以采用封闭处理室（202），可操作以在第一电极上形成钝化层的钝化层形成组件（204），以及有机半导体层形成组件（206），其可操作以形成有机半导体层在无源层上。晶圆衬底不需要从无源层形成系统转移到有机半导体层形成系统。钝化层在形成钝化层之后并且在形成有机半导体层之前不暴露于空气。结果，由于暴露于空气而导致的导电杂质不会在薄膜层中发生，因此提高了有机存储器件的生产率，质量和可靠性。系统（200）可以进一步采用可操作以在有机半导体层上形成第二电极的第二电极形成组件（208）。

9. 发明申请

WO2007041108A1 CONTACT SPACER FORMATION USING ATOMIC LAYER DEPOSITION 审中-公开
标题翻译：使用原子层沉积物接触间隙形成
公开(公告)号：WO2007041108A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/037518
申请日：2006-09-26
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , JOSHI, Amol, Ramesh , LI, Wenmei , CHENG, Ning , TAKAGI, Norimitsu , HUI, Angela, T. , AGARWAL, Ankur, Bhushan
发明人： NGO, Minh, Van , JOSHI, Amol, Ramesh , LI, Wenmei , CHENG, Ning , TAKAGI, Norimitsu , HUI, Angela, T. , AGARWAL, Ankur, Bhushan
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A contact structure in a semiconductor device includes a layer of dielectric material (410) and a via (510) formed through the dielectric material (410). The contact structure further includes a spacer (710) formed on sidewalls of the via (510) using atomic layer deposition (ALD) and a metal (905) deposited in the via (510).
摘要翻译：半导体器件中的接触结构包括介电材料层（410）和通过介电材料（410）形成的通孔（510）。接触结构还包括使用沉积在通孔（510）中的原子层沉积（ALD）和金属（905）在通孔（510）的侧壁上形成的间隔物（710）。

10. 发明申请

WO2005015635A2 SPIN ON POLYMERS FOR ORGANIC MEMORY DEVICES 审中-公开
标题翻译：自旋有机存储器装置用聚合物
公开(公告)号：WO2005015635A2
公开(公告)日：2005-02-17
申请号：PCT/US2004/006220
申请日：2004-03-01
申请人： ADVANCED MICRO DEVICES, INC. , OGLESBY, Jane, V. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , HUI, Angela, T. , NGO, Minh, Van , PANGRLE, Suzette
发明人： OGLESBY, Jane, V. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , HUI, Angela, T. , NGO, Minh, Van , PANGRLE, Suzette
IPC分类号： H01L27/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells (104) made of two electrodes (106, 108) with a controllably conductive media (110) between the two electrodes (106, 108) is disclosed. The controllably conductive media (110) contains an organic semiconductor layer (112) and passive layer (114). The organic semiconductor layer (112) is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种制造由两个电极（106,108）和两个电极（106,108）之间的可控导电介质（110）制成的有机存储单元（104）的方法。可控导电介质（110）包含有机半导体层（112）和无源层（114）。有机半导体层（112）使用旋涂技术在某些溶剂的帮助下形成。

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