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1. 发明申请

WO2007041108A1 CONTACT SPACER FORMATION USING ATOMIC LAYER DEPOSITION 审中-公开
标题翻译：使用原子层沉积物接触间隙形成
公开(公告)号：WO2007041108A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/037518
申请日：2006-09-26
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , JOSHI, Amol, Ramesh , LI, Wenmei , CHENG, Ning , TAKAGI, Norimitsu , HUI, Angela, T. , AGARWAL, Ankur, Bhushan
发明人： NGO, Minh, Van , JOSHI, Amol, Ramesh , LI, Wenmei , CHENG, Ning , TAKAGI, Norimitsu , HUI, Angela, T. , AGARWAL, Ankur, Bhushan
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A contact structure in a semiconductor device includes a layer of dielectric material (410) and a via (510) formed through the dielectric material (410). The contact structure further includes a spacer (710) formed on sidewalls of the via (510) using atomic layer deposition (ALD) and a metal (905) deposited in the via (510).
摘要翻译：半导体器件中的接触结构包括介电材料层（410）和通过介电材料（410）形成的通孔（510）。接触结构还包括使用沉积在通孔（510）中的原子层沉积（ALD）和金属（905）在通孔（510）的侧壁上形成的间隔物（710）。

2. 发明申请

WO2007015987A2 SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于改善半导体器件中的MESA宽度的系统和方法
公开(公告)号：WO2007015987A2
公开(公告)日：2007-02-08
申请号：PCT/US2006028506
申请日：2006-07-21
申请人： SPANSION LLC , ADVANCED MICRO DEVICES INC , KIM UNSOON , HUI ANGELA T , WU YIDER , CHANG KUO-TUNG , KINOSHITA HIROYUKI
发明人： KIM UNSOON , HUI ANGELA T , WU YIDER , CHANG KUO-TUNG , KINOSHITA HIROYUKI
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device ( 100) is provided. A nitride layer (330) is formed over a substrate (310). The nitride layer (330) and the substrate (310) are etched to form a trench (510). The nitride layer (330) is trimmed on opposite sides of the trench (510) to widen the trench (510) within the nitride layer (330). The trench (510) is filled with an oxide material (810). The nitride layer (330) is stripped from the memory device (100), forming a mesa (1410) above the trench (510).
摘要翻译：提供了一种用于形成存储器件（100）的方法。氮化物层（330）形成在衬底（310）上。蚀刻氮化物层（330）和衬底（310）以形成沟槽（510）。氮化物层（330）在沟槽（510）的相对侧被修整，以加宽氮化物层（330）内的沟槽（510）。沟槽（510）填充氧化物材料（810）。氮化物层（330）从存储器件（100）剥离，在沟槽（510）上方形成台面（1410）。

3. 发明申请

WO2005015635A2 SPIN ON POLYMERS FOR ORGANIC MEMORY DEVICES 审中-公开
标题翻译：自旋有机存储器装置用聚合物
公开(公告)号：WO2005015635A2
公开(公告)日：2005-02-17
申请号：PCT/US2004/006220
申请日：2004-03-01
申请人： ADVANCED MICRO DEVICES, INC. , OGLESBY, Jane, V. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , HUI, Angela, T. , NGO, Minh, Van , PANGRLE, Suzette
发明人： OGLESBY, Jane, V. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , HUI, Angela, T. , NGO, Minh, Van , PANGRLE, Suzette
IPC分类号： H01L27/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells (104) made of two electrodes (106, 108) with a controllably conductive media (110) between the two electrodes (106, 108) is disclosed. The controllably conductive media (110) contains an organic semiconductor layer (112) and passive layer (114). The organic semiconductor layer (112) is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种制造由两个电极（106,108）和两个电极（106,108）之间的可控导电介质（110）制成的有机存储单元（104）的方法。可控导电介质（110）包含有机半导体层（112）和无源层（114）。有机半导体层（112）使用旋涂技术在某些溶剂的帮助下形成。

4. 发明申请

WO2005074023A1 METHOD OF FORMING PLANARIZED SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：形成平面浅层分离分离方法
公开(公告)号：WO2005074023A1
公开(公告)日：2005-08-11
申请号：PCT/US2004/043108
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES, INC. , CHAN, Darin, A. , CHAN, Simon, S. , HUI, Angela, T.
发明人： CHAN, Darin, A. , CHAN, Simon, S. , HUI, Angela, T.
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill (25) with respect to the polish stop film (23) prior to removing the polish stop film (23). Embodiments include etching back a silicon oxide trench fill (25) to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer (23) leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.
摘要翻译：在去除抛光停止膜（23）之前，通过相对于抛光停止膜（23）选择性地蚀刻介质沟槽填充物（25）来形成具有最小化形貌的平坦化STI。实施例包括将氧化硅沟槽填充物（25）刻蚀至约至大约的深度，然后剥离留下基本平坦化表面的氮化硅抛光停止层（23），从而提高后续栅电极的精度图案化和缩小桁条。

5. 发明申请

WO2004073047A3 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存存储器件在紫外线诱发充电中的紫外线阻挡层
公开(公告)号：WO2004073047A3
公开(公告)日：2004-10-07
申请号：PCT/US2004000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES INC , NGO MINH VAN , KAMAL TAZRIEN , RAMSBEY MARK T , HALLIYAL ARVIND , PARK JAEYONG , CHENG NING , ERHARDT JEFF P , SHIELDS JEFFREY A , FERGUSON CLARENCE , HUI ANGELA T , HUERTAS ROBERT A , GOTTIPATI TYAGAMOHAN
发明人： NGO MINH VAN , KAMAL TAZRIEN , RAMSBEY MARK T , HALLIYAL ARVIND , PARK JAEYONG , CHENG NING , ERHARDT JEFF P , SHIELDS JEFFREY A , FERGUSON CLARENCE , HUI ANGELA T , HUERTAS ROBERT A , GOTTIPATI TYAGAMOHAN
IPC分类号： H01L21/28 , H01L21/336 , H01L23/552 , H01L27/115 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS闪存单元（24）免受UV感应充电的方法，包括在半导体器件（10,50）中制造SONOS闪存单元（24）; 以及在所述SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上不透紫外线的材料。一种包括SONOS闪速存储器单元（24）的SONOS闪速存储器件（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上不透紫外线的材料。

6. 发明申请

WO2005074018A1 STRUCTURE AND METHOD FOR LOW VSS RESISITANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL 审中-公开
标题翻译：浮动栅格存储单元中低VSS电阻和减少的数据库的结构和方法
公开(公告)号：WO2005074018A1
公开(公告)日：2005-08-11
申请号：PCT/US2004/042870
申请日：2004-12-17
申请人： SPANSION LLC , FANG, Shenqing , THURGATE, Timothy , CHANG, Kuo-Tung , FASTOW, Richard , HUI, Angela, T. , MIZUTANI, Kazuhiro , KO, Kelwin , KINOSHITA, Hiroyuki , SUN, Yu , OGAWA, Hiroyuki
发明人： FANG, Shenqing , THURGATE, Timothy , CHANG, Kuo-Tung , FASTOW, Richard , HUI, Angela, T. , MIZUTANI, Kazuhiro , KO, Kelwin , KINOSHITA, Hiroyuki , SUN, Yu , OGAWA, Hiroyuki
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell (202) comprises a stacked gate structure (208) situated on a substrate (204) and situated over a channel region (222) in the substrate (204). The floating gate memory cell (202) further comprises a recess (228) formed in the substrate (204) adjacent to the stacked gate structure (208), where the recess (228) has a sidewall (230), a bottom (232), and a depth (236). According to this exemplary embodiment, the floating gate memory cell (202) further comprises a source (234) situated adjacent to the sidewall (230) of the recess (228) and under the stacked gate structure (208). The floating gate memory cell (202) further comprises a Vss connection region (238) situated under the bottom (232) of the recess (228) and under the source (234), where the Vss connection region (238) is connected to the source (234). The Vss connection region (238) being situated under the bottom (232) of the recess (228) causes the source (234) to have a reduced lateral diffusion in the channel region (222).
摘要翻译：根据一个示例性实施例，浮动栅极存储单元（202）包括位于衬底（204）上且位于衬底（204）中的沟道区域（222）之上的层叠栅极结构（208）。浮动栅极存储单元（202）还包括形成在与堆叠的栅极结构（208）相邻的衬底（204）中的凹部（228），其中凹部（228）具有侧壁（230），底部（232），和深度（236）。根据该示例性实施例，浮动栅极存储单元（202）还包括位于与凹部（228）的侧壁（230）相邻并位于堆叠栅极结构（208）下方的源极（234）。浮动栅极存储单元（202）还包括位于凹部（228）的底部（232）下方并且在源极（234）下方的Vss连接区域（238），其中Vss连接区域（238）连接到来源（234）。位于凹部（228）的底部（232）下面的Vss连接区域（238）使得源极（234）在沟道区域（222）中具有减小的横向扩散。

7. 发明申请

WO2004073047A2 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存器件在BEOL加工中紫外线诱导充电的紫外线阻挡层
公开(公告)号：WO2004073047A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
发明人： NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
IPC分类号： H01L
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS快闪存储单元（24）不受紫外线感应充电的方法，包括在半导体器件（10,50）中制造SONOS快闪存储单元（24）; 以及在SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上UV不透明材料。包括SONOS闪存单元（24）的SONOS闪存设备（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上UV不透明材料。

8. 发明申请

WO2007047265A1 BIT LINE IMPLANT 审中-公开
标题翻译：位线植入
公开(公告)号：WO2007047265A1
公开(公告)日：2007-04-26
申请号：PCT/US2006/039547
申请日：2006-10-06
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , YANG, Jean , SUN, Yu , RAMSBEY, Mark T. , WEIDONG, Qian , HUI, Angela T.
发明人： YANG, Jean , SUN, Yu , RAMSBEY, Mark T. , WEIDONG, Qian , HUI, Angela T.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures (1410) on an oxide-nitride-oxide stack (1220, 1230, 1240) of a semiconductor device (1200). Each structure of the group of structures includes a polysilicon portion (1250) and a hard mask portion (1260). A first structure (1410) of the group of structures is separated from a second structure (1410) of the group of structures by less than 100 nanometers. The method further includes using the first structure (1410) and the second structure (1410) to isolate a portion of the semiconductor device (1200) for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件（1200）的氧化物 - 氮化物 - 氧化物堆叠（1220,1230,1240）上形成一组结构（1410）。该组结构的每个结构包括多晶硅部分（1250）和硬掩模部分（1260）。该组结构的第一结构（1410）与该组结构的第二结构（1410）分开小于100纳米。该方法还包括使用第一结构（1410）和第二结构（1410）来隔离位线植入物的半导体器件（1200）的一部分。

9. 发明申请

WO2007015987A3 SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2007015987A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/028506
申请日：2006-07-21
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , KIM, Unsoon , HUI, Angela, T. , WU, Yider , CHANG, Kuo-tung , KINOSHITA, Hiroyuki
发明人： KIM, Unsoon , HUI, Angela, T. , WU, Yider , CHANG, Kuo-tung , KINOSHITA, Hiroyuki
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L27/105
摘要： A method for forming a memory device ( 100) is provided. A nitride layer (330) is formed over a substrate (310). The nitride layer (330) and the substrate (310) are etched to form a trench (510). The nitride layer (330) is trimmed on opposite sides of the trench (510) to widen the trench (510) within the nitride layer (330). The trench (510) is filled with an oxide material (810). The nitride layer (330) is stripped from the memory device (100), forming a mesa (1410) above the trench (510).

10. 发明申请

WO2005104187A1 IN-SITU SURFACE TREATMENT FOR MEMORY CELL FORMATION 审中-公开
标题翻译：用于记忆细胞形成的现场表面处理
公开(公告)号：WO2005104187A1
公开(公告)日：2005-11-03
申请号：PCT/US2005/004654
申请日：2005-02-11
申请人： ADVANCED MICRO DEVICES, INC. , HUI, Angela, T.
发明人： HUI, Angela, T.
IPC分类号： H01L21/00
CPC分类号： H01L21/67069
摘要： A system and methodology are disclosed for forming a passive layer on a conductive layer, such as can be done during fabrication of an organic memory cell, which generally mitigates drawbacks inherent in conventional inorganic memory devices. The passive layer includes a conductivity facilitating compound, such as copper sulfide (Cu 2 S), which is generated from an upper portion of a conductive material. The conductive material can serve as a bottom electrode in the memory cell, and the upper portion of the conductive material can be transformed into the passive layer via treatment with a plasma generated from fluorine (F) based gases.
摘要翻译：公开了用于在导电层上形成钝化层的系统和方法，例如可以在制造有机存储器单元期间完成，这通常减轻了常规无机存储器件固有的缺点。钝化层包括从导电材料的上部产生的导电性促进化合物，例如硫化铜（Cu2S）。导电材料可以用作存储单元中的底部电极，并且导电材料的上部可以通过用基于氟（F）的气体产生的等离子体处理而转化为钝化层。

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