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1. 发明申请

WO2005103828A2 SYSTEM AND METHOD FOR FABRICATING CONTACT HOLES 审中-公开
标题翻译：用于制造接触孔的系统和方法
公开(公告)号：WO2005103828A2
公开(公告)日：2005-11-03
申请号：PCT/US2005/007302
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES, INC. , MINVIELLE, Anna, M. , TABERY, Cyrus, E. , KIM, Hung-Eil , KYE, Jongwook
发明人： MINVIELLE, Anna, M. , TABERY, Cyrus, E. , KIM, Hung-Eil , KYE, Jongwook
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes (20, 2) of varying pitch and density in a contact layer (56) of an integrated circuit device (10) is provided. The plurality of contact holes (20, 24) can include a plurality of regularly spaced contact holes (20) having a first pitch along a first direction and a plurality of semi-isolated contact holes (24) having a second pitch along a second direction. A double-dipole illumination source (42, 44) can transmit light energy through a mask (48) having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source (42, 44) can include a first dipole aperture (60), which is oriented and optimized for patterning the regularly spaced contact holes (20), and a second dipole aperture (62), which is oriented substantially orthogonal to the first dipole aperture (60) and optimized for patterning the plurality of semi-isolated contact holes (24). The contact layer (56) can be etched using the patterned photoresist layer (58).
摘要翻译：提供了一种在集成电路器件（10）的接触层（56）中形成多个具有变化的间距和密度的接触孔（20,2）的方法。多个接触孔（20,24）可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔（20）和沿第二方向具有第二间距的多个半隔离接触孔（24）。双偶极子照明源（42,44）可通过具有对应于期望的接触孔图案的图案的掩模（48）传输光能。双偶极子照明源（42,44）可以包括第一偶极孔（60），其被定向和优化用于图案化规则间隔的接触孔（20）和第二偶极孔（62），第二偶极孔与第一偶极孔（60）正交并且被优化用于图案化多个半隔离接触孔（24）。可以使用图案化的光致抗蚀剂层（58）来蚀刻接触层（56）。

2. 发明申请

WO2005104189A3 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 审中-公开
公开(公告)号：WO2005104189A3
公开(公告)日：2005-11-03
申请号：PCT/US2005/007301
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES, INC. , TABERY, Cyrus, E. , LUKANC, Todd, P. , HAIDINYAK, Chris , CAPODIECI, Luigi , BABCOCK, Carl, P. , KIM, Hung-Eil , SPENCE, Christopher, A.
发明人： TABERY, Cyrus, E. , LUKANC, Todd, P. , HAIDINYAK, Chris , CAPODIECI, Luigi , BABCOCK, Carl, P. , KIM, Hung-Eil , SPENCE, Christopher, A.
IPC分类号： G03F7/20
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout (300) on a wafer includes simulating (310) how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified (320) based on manufacturability. RETs that provide optimal manufacturability can be selected (330). In this manner, the simulation tool (210) can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

3. 发明申请

WO2003036701A1 LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS 审中-公开
标题翻译：低温后激活过程
公开(公告)号：WO2003036701A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/032555
申请日：2002-10-11
申请人： ADVANCED MICRO DEVICES, INC. , YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
发明人： YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
IPC分类号： H01L21/268
CPC分类号： H01L29/665 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode (24) over a substrate (10) and a gate oxide (16) between the gate electrode (24) and the substrate (10); forming source/drain extensions (30, 32) in the substrate (10); forming first and second sidewall spacers (36, 38); implanting dopants (44) within the substrate (10) to form source/drain regions (40, 42) in the substrate (10) adjacent to the sidewalls spacers (36, 38); laser thermal annealing to activate the source/drain regions (40, 42); depositing a layer of nickel (46) over the source/drain regions (40, 42); and annealing to form a nickel silicide layer (46) disposed on the source/drain regions (40, 42). The source/drain extensions (30, 32) and sidewall spacers (36, 38) are adjacent to the gate electrode (24). The source/drain extensions (30, 32) can have a depth of about 5 to 30 nanometers, and the source/drain regions (40, 42) can have a depth of about 40 to 100 nanometers. The annealing is at temperatures from about 350 to 500 °C.
摘要翻译：一种制造MOSFET半导体器件的方法包括在栅电极（24）和衬底（10）之间的衬底（10）和栅氧化层（16）上形成栅电极（24）。在所述衬底（10）中形成源极/漏极延伸部（30,32）; 形成第一和第二侧壁间隔件（36,38）; 在所述衬底（10）内注入掺杂剂（44）以在所述衬底（10）中邻近所述侧壁间隔物（36,38）形成源/漏区（40,42）; 激光热退火以激活源/漏区（40,42）; 在源/漏区（40,42）上沉积一层镍（46）; 和退火以形成设置在源/漏区（40,42）上的硅化镍层（46）。源极/漏极延伸部（30,32）和侧壁间隔物（36,38）与栅电极（24）相邻。源极/漏极扩展部（30,32）可以具有约5至30纳米的深度，并且源极/漏极区域（40,42）可以具有约40至100纳米的深度。退火温度在约350-500℃

4. 发明申请

WO2005048339A1 SELF ALIGNED DAMASCENE GATE 审中-公开
标题翻译：自对准丹麦门
公开(公告)号：WO2005048339A1
公开(公告)日：2005-05-26
申请号：PCT/US2004/033251
申请日：2004-10-08
申请人： ADVANCED MICRO DEVICES, INC. , TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
发明人： TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320) to expose a channel area (330) of the MOSFET (200), etching the fin (310) to thin a width of the fin (310) in the channel area (330), forming a gate over the fin (310), and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种用于形成金属氧化物半导体场效应晶体管（200）的方法，包括在衬底上形成翅片区域，源极区域和漏极区域，在翅片区域形成翅片（310），并形成在翅片区域中的掩模（320）。该方法还包括蚀刻掩模（320）以暴露MOSFET（200）的沟道区域（330），蚀刻鳍片（310）以使沟槽区域（330）中的鳍片（310）的宽度变薄，从而形成在所述翅片（310）上方的栅极，以及形成与所述栅极，所述源极区域和所述漏极区域的接触。

5. 发明申请

WO2005022266A2 METHOD AND APPARATUS FOR ELIMINATION OF BUBBLES IN IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY SYSTEMS 审中-公开
标题翻译：用于消除浸没式离心系统中浸没介质中的泡沫的方法和装置
公开(公告)号：WO2005022266A2
公开(公告)日：2005-03-10
申请号：PCT/US2004/028371
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC. , PAWLOSKI, Adam, R. , ADO, Amr, Y. , AMBLARD, Gilles, R. , LAFONTAINE, Bruno, M. , LALOVIC, Ivan , LEVINSON, Harry, J. , SCHEFSKE, Jeffrey, A. , TABERY, Cyrus, E. , TSAI, Frank
发明人： PAWLOSKI, Adam, R. , ADO, Amr, Y. , AMBLARD, Gilles, R. , LAFONTAINE, Bruno, M. , LALOVIC, Ivan , LEVINSON, Harry, J. , SCHEFSKE, Jeffrey, A. , TABERY, Cyrus, E. , TSAI, Frank
IPC分类号： G03F7/20
CPC分类号： G03F7/70341
摘要： A method of operating an immersion lithography system (26), including steps of immersing at least a portion of a wafer (12) to be exposed in an immersion medium (24), wherein the immersion medium comprises at least one bubble (28); directing an ultrasonic wave (36) through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern (22) by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system (30, 32, 34) for an immersion lithography system (26).
摘要翻译：一种操作浸没式光刻系统（26）的方法，包括将要曝光的晶片（12）的至少一部分浸入浸没介质（24）中的步骤，其中浸入介质包括至少一个气泡（28）; 引导超声波（36）穿过所述浸没介质的至少一部分以破坏和/或消散所述至少一个气泡; 以及通过在导向之后通过电磁辐射穿过浸渍介质，用曝光图案（22）曝光晶片。还公开了一种用于浸没式光刻系统（26）的监视和控制系统（30,32,34）。

6. 发明申请

WO2004006014A2 METHOD OF USING AN AMORPHOUS CARBON LAYER FOR IMPROVED RETICLE FABRICATION 审中-公开
标题翻译：使用非晶碳层改善制造方法
公开(公告)号：WO2004006014A2
公开(公告)日：2004-01-15
申请号：PCT/US2003/020113
申请日：2003-06-25
申请人： ADVANCED MICRO DEVICES, INC.
发明人： TABERY, Cyrus, E. , LYONS, Christopher, F.
IPC分类号： G03F1/08
CPC分类号： G03F1/54 , G03F1/76
摘要： A method of using an amorphous carbon layer (130) for improved reticle fabrication includes depositing a stack of layers including a substrate (110), an absorber (120), a transfer layer (130), an antireflective coating (ARC) layer (140), and a photoresist layer (150), patterning (45) the photoresist layer (150), and etching (55, 65) the ARC layer (140) and the transfer layer (130). The method also includes etching (75) the absorber layer(120) and removing (85) the transfer layer (130). The transfer layer (130) including amorphous carbon.
摘要翻译：使用非晶碳层（130）用于改进的掩模版制造的方法包括沉积包括基底（110），吸收体（120），转移层（130），抗反射涂层（ARC）层（140））和光致抗蚀剂层（150），图案化（45）光致抗蚀剂层（150），以及蚀刻（55,65）ARC层（140）和转移层（130）。该方法还包括蚀刻（75）吸收层（120）并去除（85）转移层（130）。转移层（130）包括无定形碳。

7. 发明申请

WO2004044973A1 PLANARIZING GATE MATERIAL TO IMPROVE GATE CRITICAL DIMENSION IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：平面化材料在半导体器件中提高栅极关键尺寸
公开(公告)号：WO2004044973A1
公开(公告)日：2004-05-27
申请号：PCT/US2003/032655
申请日：2003-10-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： AHMED, Shibly, S. , TABERY, Cyrus, E. , WANG, Haihong , YU, Bin
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7853
摘要： A method of manufacturing a semiconductor device (100) may include forming a fin structure (210) on an insulator (120). The fin structure (210) may include side surfaces and a top surface. The method may also include depositing a gate material (320) over the fin structure (210) and planarizing the deposited gate material (320). An antireflective coating (520) may be deposited on the planarized gate material (320), and a gate structure (510) may be formed out of the planarized gate material (320) using the antireflective coating (520).
摘要翻译：制造半导体器件（100）的方法可以包括在绝缘体（120）上形成翅片结构（210）。翅片结构（210）可以包括侧表面和顶表面。该方法还可以包括在鳍结构（210）上沉积栅极材料（320）并平坦化沉积的栅极材料（320）。可以在平坦化的栅极材料（320）上沉积抗反射涂层（520），并且可以使用抗反射涂层（520）从平坦化栅极材料（320）形成栅极结构（510）。

8. 发明申请

WO2004038808A2 DOUBLE AND TRIPLE GATE MOSFET DEVICES AND METHODS FOR MAKING SAME 审中-公开
标题翻译：双和三极门MOSFET器件及其制造方法
公开(公告)号：WO2004038808A2
公开(公告)日：2004-05-06
申请号：PCT/US2003/032660
申请日：2003-10-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LIN, Ming-Ren , AN, Judy, Xilin , KRIVOKAPIC, Zoran , TABERY, Cyrus, E. , WANG, Haihong , YU, Bin
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/66818
摘要： A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin (220), a first gate (240) and a second gate (420). The first gate (240) is formed on top of the fin (220). The second gate (420) surrounds the fin (220) and the first gate (240). In another implementation, a triple gate MOSFET includes a fin (220), a first gate (710), a second gate (720), and a third gate (730). The first gate (710) is formed on top of the fin (220). The second gate (720) is formed adjacent the fin (220). The third gate (730) is formed adjacent the fin (220) and opposite the second gate (720).
摘要翻译：双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍（220），第一栅极（240）和第二栅极（420）。第一门（240）形成在翅片（220）的顶部。第二门（420）包围翅片（220）和第一门（240）。在另一实施方案中，三栅极MOSFET包括鳍片（220），第一栅极（710），第二栅极（720）和第三栅极（730）。第一门（710）形成在翅片（220）的顶部。第二门（720）形成在翅片（220）附近。第三门（730）与翅片（220）相邻并与第二门（720）相对地形成。

9. 发明申请

WO2003026000A1 IN-SITU OR EX-SITU PROFILE MONITORING OF PHASE OPENINGS ON ALTERNATING PHASE SHIFTING MASKS BY SCATTEROMETRY 审中-公开
标题翻译：现场或现场配置文件通过散射表测量相位切换面板上的相位开关监视
公开(公告)号：WO2003026000A1
公开(公告)日：2003-03-27
申请号：PCT/US2002/010826
申请日：2002-04-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： TABERY, Cyrus, E. , PHAN, Khoi, A. , RANGARAJAN, Bharath , SINGH, Bhanwar , SUBRAMANIAN, Ramkumar
IPC分类号： H01L21/66
CPC分类号： G03F1/30 , G01N21/47
摘要： A system for monitoring and controlling aperture etching in an alternating aperture phase shift mask (170, 270, 370, 722) is provided. The system includes one or more light sources (744, 762, 844), each light source (744, 762, 844) directing light to one or more apertures (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) etched on a mask (420, 922). Light reflected from the apertures (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) is collected by a measuring system (750, 850), which processes the collected light. The collected light is indicative of properties including the depth, width and/or profile of the openings on the mask (420, 922). The measuring system (750, 850) provides such depth, width and/or profile related data to a processor (760, 860, 1210) that determines the acceptability of the aperture (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) and/or the mask (420, 922). The system also includes a plurality of etching devices (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) in the mask (420, 922). The processor (760, 860, 1210) may selectively control the etching devices (450, 480) so as to regulate aperture etching.
摘要翻译：提供了一种用于在交替孔径相移掩模（170,270,370,722）中监测和控制孔隙蚀刻的系统。该系统包括一个或多个光源（744,762,844），每个光源（744,762,844）将光引导到一个或多个孔（150,160,250,260,350,360,430,504， 506,408,604,610,612,724,824,924）蚀刻在掩模（420,922）上。从孔（150,160,250,260,350,360,430,504,506,508,604,610,612,724,824,924）反射的光由测量系统（750,850）收集，它处理收集的光。所收集的光指示包括掩模（420,922）上的开口的深度，宽度和/或轮廓的特性。测量系统（750,850）向处理器（760,860,1210）提供这样的深度，宽度和/或轮廓相关数据，该处理器确定孔的可接受性（150,160,250,260,350,360,430 ，504,506,508,604,610,612,724,824,924）和/或掩模（420,922）。该系统还包括掩模（420,922）中的多个蚀刻装置（150,160,250,260,350,360,430,504,506,508,604,610,612,724,824,924）。处理器（760,860,1210）可以选择性地控制蚀刻装置（450,480），以调节孔径蚀刻。

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