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1. 发明申请

WO2005104189A3 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 审中-公开
公开(公告)号：WO2005104189A3
公开(公告)日：2005-11-03
申请号：PCT/US2005/007301
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES, INC. , TABERY, Cyrus, E. , LUKANC, Todd, P. , HAIDINYAK, Chris , CAPODIECI, Luigi , BABCOCK, Carl, P. , KIM, Hung-Eil , SPENCE, Christopher, A.
发明人： TABERY, Cyrus, E. , LUKANC, Todd, P. , HAIDINYAK, Chris , CAPODIECI, Luigi , BABCOCK, Carl, P. , KIM, Hung-Eil , SPENCE, Christopher, A.
IPC分类号： G03F7/20
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout (300) on a wafer includes simulating (310) how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified (320) based on manufacturability. RETs that provide optimal manufacturability can be selected (330). In this manner, the simulation tool (210) can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

2. 发明申请

WO2003036701A1 LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS 审中-公开
标题翻译：低温后激活过程
公开(公告)号：WO2003036701A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/032555
申请日：2002-10-11
申请人： ADVANCED MICRO DEVICES, INC. , YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
发明人： YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
IPC分类号： H01L21/268
CPC分类号： H01L29/665 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode (24) over a substrate (10) and a gate oxide (16) between the gate electrode (24) and the substrate (10); forming source/drain extensions (30, 32) in the substrate (10); forming first and second sidewall spacers (36, 38); implanting dopants (44) within the substrate (10) to form source/drain regions (40, 42) in the substrate (10) adjacent to the sidewalls spacers (36, 38); laser thermal annealing to activate the source/drain regions (40, 42); depositing a layer of nickel (46) over the source/drain regions (40, 42); and annealing to form a nickel silicide layer (46) disposed on the source/drain regions (40, 42). The source/drain extensions (30, 32) and sidewall spacers (36, 38) are adjacent to the gate electrode (24). The source/drain extensions (30, 32) can have a depth of about 5 to 30 nanometers, and the source/drain regions (40, 42) can have a depth of about 40 to 100 nanometers. The annealing is at temperatures from about 350 to 500 °C.
摘要翻译：一种制造MOSFET半导体器件的方法包括在栅电极（24）和衬底（10）之间的衬底（10）和栅氧化层（16）上形成栅电极（24）。在所述衬底（10）中形成源极/漏极延伸部（30,32）; 形成第一和第二侧壁间隔件（36,38）; 在所述衬底（10）内注入掺杂剂（44）以在所述衬底（10）中邻近所述侧壁间隔物（36,38）形成源/漏区（40,42）; 激光热退火以激活源/漏区（40,42）; 在源/漏区（40,42）上沉积一层镍（46）; 和退火以形成设置在源/漏区（40,42）上的硅化镍层（46）。源极/漏极延伸部（30,32）和侧壁间隔物（36,38）与栅电极（24）相邻。源极/漏极扩展部（30,32）可以具有约5至30纳米的深度，并且源极/漏极区域（40,42）可以具有约40至100纳米的深度。退火温度在约350-500℃

3. 发明申请

WO2005104189A2 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 审中-公开
标题翻译：使用光学规则检查分辨率增强技术的集成电路设备和制造的系统和方法
公开(公告)号：WO2005104189A2
公开(公告)日：2005-11-03
申请号：PCT/US2005007301
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES INC , TABERY CYRUS E , LUKANC TODD P , HAIDINYAK CHRIS , CAPODIECI LUIGI , BABCOCK CARL P , KIM HUNG-EIL , SPENCE CHRISTOPHER A
发明人： TABERY CYRUS E , LUKANC TODD P , HAIDINYAK CHRIS , CAPODIECI LUIGI , BABCOCK CARL P , KIM HUNG-EIL , SPENCE CHRISTOPHER A
IPC分类号： G03F7/20 , H01L21/00
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout (300) on a wafer includes simulating (310) how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified (320) based on manufacturability. RETs that provide optimal manufacturability can be selected (330). In this manner, the simulation tool (210) can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上图案化布局（300）的多个光刻工艺参数的方法包括模拟（310）布局将如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局内的结构边缘可以基于可制造性进行分类（320）。可以选择提供最佳可制造性的RET（330）。以这种方式，模拟工具（210）可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

4. 发明申请

WO2005048339A1 SELF ALIGNED DAMASCENE GATE 审中-公开
标题翻译：自对准丹麦门
公开(公告)号：WO2005048339A1
公开(公告)日：2005-05-26
申请号：PCT/US2004/033251
申请日：2004-10-08
申请人： ADVANCED MICRO DEVICES, INC. , TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
发明人： TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320) to expose a channel area (330) of the MOSFET (200), etching the fin (310) to thin a width of the fin (310) in the channel area (330), forming a gate over the fin (310), and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种用于形成金属氧化物半导体场效应晶体管（200）的方法，包括在衬底上形成翅片区域，源极区域和漏极区域，在翅片区域形成翅片（310），并形成在翅片区域中的掩模（320）。该方法还包括蚀刻掩模（320）以暴露MOSFET（200）的沟道区域（330），蚀刻鳍片（310）以使沟槽区域（330）中的鳍片（310）的宽度变薄，从而形成在所述翅片（310）上方的栅极，以及形成与所述栅极，所述源极区域和所述漏极区域的接触。

5. 发明申请

WO2005103828A3 SYSTEM AND METHOD FOR FABRICATING CONTACT HOLES 审中-公开
标题翻译：用于制作接触孔的系统和方法
公开(公告)号：WO2005103828A3
公开(公告)日：2006-06-29
申请号：PCT/US2005007302
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES INC , MINVIELLE ANNA M , TABERY CYRUS E , KIM HUNG-EIL , KYE JONGWOOK
发明人： MINVIELLE ANNA M , TABERY CYRUS E , KIM HUNG-EIL , KYE JONGWOOK
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes (20, 24) of varying pitch and density in a contact layer (56) of an integrated circuit device (10) is provided . The plurality of contact holes (20, 24) can include a plurality of regularly spaced contact holes (20) having a first pitch along a first direction and a plurality of semi-isolated contact holes (24) having a second pitch along a second direction. A double-dipole illumination source (42, 44) can transmit light energy through a mask (48) having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source (42, 44) can include a first dipole aperture (60), which is oriented and optimized for patterning the regularly spaced contact holes (20), and a second dipole aperture (62), which is oriented substantially orthogonal to the first dipole aperture (60) and optimized for patterning the plA method of forming a plurality of contact holes (20, 2) of varying pitch and density in a contact layer (56) of an integrated circuit device (10) is provided. The plurality of contact holes (20, 24) can include a plurality of regularly spaced contact holes (20) having a first pitc along a first direction and a plurality of semi-isolated contact holes (24) having a second pitch along a second direction. A double-dipole illumination source (42, 44) can transmit light energy through a mask (48) having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source (42, 44) can include a first dipole aperture (60), which is oriented and optimized for patterning the regularly spaced contact holes (20), and a second dipole aperture (62), which is oriented substantially orthogonal to the first dipole aperture (60) and optimized for patterning the plurality of semi-isolated contact holes (24). The contact layer (56) can be etched using the patterned photoresist layer (58).
摘要翻译：提供一种在集成电路器件（10）的接触层（56）中形成多个具有变化的间距和密度的接触孔（20,24）的方法。多个接触孔（20,24）可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔（20）和沿第二方向具有第二间距的多个半隔离接触孔（24）。双偶极子照明源（42,44）可通过具有对应于期望的接触孔图案的图案的掩模（48）透射光能。双偶极子照明源（42,44）可以包括第一偶极孔（60），其被定向和优化以用于图案化规则间隔开的接触孔（20），以及第二偶极孔（62），其基本上定向提供与第一偶极子孔（60）正交并且被优化用于图案化在集成电路装置（10）的接触层（56）中形成具有变化的间距和密度的多个接触孔（20,2）的plA方法。多个接触孔（20,24）可以包括沿着第一方向具有第一凹坑的多个规则间隔的接触孔（20）和沿着第二方向具有第二间距的多个半隔离接触孔（24）。双偶极子照明源（42,44）可通过具有对应于期望的接触孔图案的图案的掩模（48）透射光能。双偶极子照明源（42,44）可以包括第一偶极孔（60），其被定向和优化以用于图案化规则间隔开的接触孔（20），以及第二偶极孔（62），其基本上定向与第一偶极孔（60）正交并且被优化用于图案化多个半隔离接触孔（24）。可以使用图案化的光致抗蚀剂层（58）来蚀刻接触层（56）。

6. 发明申请

WO2005103828A2 SYSTEM AND METHOD FOR FABRICATING CONTACT HOLES 审中-公开
标题翻译：用于制造接触孔的系统和方法
公开(公告)号：WO2005103828A2
公开(公告)日：2005-11-03
申请号：PCT/US2005/007302
申请日：2005-03-07
申请人： ADVANCED MICRO DEVICES, INC. , MINVIELLE, Anna, M. , TABERY, Cyrus, E. , KIM, Hung-Eil , KYE, Jongwook
发明人： MINVIELLE, Anna, M. , TABERY, Cyrus, E. , KIM, Hung-Eil , KYE, Jongwook
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes (20, 2) of varying pitch and density in a contact layer (56) of an integrated circuit device (10) is provided. The plurality of contact holes (20, 24) can include a plurality of regularly spaced contact holes (20) having a first pitch along a first direction and a plurality of semi-isolated contact holes (24) having a second pitch along a second direction. A double-dipole illumination source (42, 44) can transmit light energy through a mask (48) having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source (42, 44) can include a first dipole aperture (60), which is oriented and optimized for patterning the regularly spaced contact holes (20), and a second dipole aperture (62), which is oriented substantially orthogonal to the first dipole aperture (60) and optimized for patterning the plurality of semi-isolated contact holes (24). The contact layer (56) can be etched using the patterned photoresist layer (58).
摘要翻译：提供了一种在集成电路器件（10）的接触层（56）中形成多个具有变化的间距和密度的接触孔（20,2）的方法。多个接触孔（20,24）可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔（20）和沿第二方向具有第二间距的多个半隔离接触孔（24）。双偶极子照明源（42,44）可通过具有对应于期望的接触孔图案的图案的掩模（48）传输光能。双偶极子照明源（42,44）可以包括第一偶极孔（60），其被定向和优化用于图案化规则间隔的接触孔（20）和第二偶极孔（62），第二偶极孔与第一偶极孔（60）正交并且被优化用于图案化多个半隔离接触孔（24）。可以使用图案化的光致抗蚀剂层（58）来蚀刻接触层（56）。

7. 发明申请

WO2005022266A3 IMMERSION MEDIUM BUBBLE ELIMINATION IN IMMERSION LITHOGRAPHY 审中-公开
标题翻译：浸入式沉积中的中等泡沫消除
公开(公告)号：WO2005022266A3
公开(公告)日：2005-09-01
申请号：PCT/US2004028371
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES INC , PAWLOSKI ADAM R , ADO AMR Y , AMBLARD GILLES R , LAFONTAINE BRUNO M , LALOVIC IVAN , LEVINSON HARRY J , SCHEFSKE JEFFREY A , TABERY CYRUS E , TSAI FRANK
发明人： PAWLOSKI ADAM R , ADO AMR Y , AMBLARD GILLES R , LAFONTAINE BRUNO M , LALOVIC IVAN , LEVINSON HARRY J , SCHEFSKE JEFFREY A , TABERY CYRUS E , TSAI FRANK
IPC分类号： G03F7/20
CPC分类号： G03F7/70341
摘要： A method of operating an immersion lithography system (26), including steps of immersing at least a portion of a wafer (12) to be exposed in an immersion medium (24), wherein the immersion medium comprises at least one bubble (28); directing an ultrasonic wave (36) through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern (22) by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system (30, 32, 34) for an immersion lithography system (26).
摘要翻译：一种操作浸没式光刻系统（26）的方法，包括将要曝光的晶片（12）的至少一部分浸入浸没介质（24）中的步骤，其中浸没介质包括至少一个气泡（28）; 引导超声波（36）穿过所述浸没介质的至少一部分以破坏和/或消散所述至少一个气泡; 以及通过在导向之后通过电磁辐射穿过浸渍介质，用曝光图案（22）曝光晶片。还公开了一种用于浸没式光刻系统（26）的监视和控制系统（30,32,34）。

8. 发明申请

WO2005022266A2 METHOD AND APPARATUS FOR ELIMINATION OF BUBBLES IN IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY SYSTEMS 审中-公开
标题翻译：用于消除浸没式离心系统中浸没介质中的泡沫的方法和装置
公开(公告)号：WO2005022266A2
公开(公告)日：2005-03-10
申请号：PCT/US2004/028371
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC. , PAWLOSKI, Adam, R. , ADO, Amr, Y. , AMBLARD, Gilles, R. , LAFONTAINE, Bruno, M. , LALOVIC, Ivan , LEVINSON, Harry, J. , SCHEFSKE, Jeffrey, A. , TABERY, Cyrus, E. , TSAI, Frank
发明人： PAWLOSKI, Adam, R. , ADO, Amr, Y. , AMBLARD, Gilles, R. , LAFONTAINE, Bruno, M. , LALOVIC, Ivan , LEVINSON, Harry, J. , SCHEFSKE, Jeffrey, A. , TABERY, Cyrus, E. , TSAI, Frank
IPC分类号： G03F7/20
CPC分类号： G03F7/70341
摘要： A method of operating an immersion lithography system (26), including steps of immersing at least a portion of a wafer (12) to be exposed in an immersion medium (24), wherein the immersion medium comprises at least one bubble (28); directing an ultrasonic wave (36) through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern (22) by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system (30, 32, 34) for an immersion lithography system (26).
摘要翻译：一种操作浸没式光刻系统（26）的方法，包括将要曝光的晶片（12）的至少一部分浸入浸没介质（24）中的步骤，其中浸入介质包括至少一个气泡（28）; 引导超声波（36）穿过所述浸没介质的至少一部分以破坏和/或消散所述至少一个气泡; 以及通过在导向之后通过电磁辐射穿过浸渍介质，用曝光图案（22）曝光晶片。还公开了一种用于浸没式光刻系统（26）的监视和控制系统（30,32,34）。

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