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1. 发明申请

WO2003054964A2 MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE 审中-公开
标题翻译：带有金属硅化物线的MONOS器件
公开(公告)号：WO2003054964A2
公开(公告)日：2003-07-03
申请号：PCT/US2002/039781
申请日：2002-12-11
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： OGURA, Jusuke , RAMSBEY, Mark, T. , HALLIYAL, Arvind , KRIVOKAPIC, Zoran , NGO, Minh, Van , TRIPSAS, Nicholas, H.
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L21/743 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer (32), such as an oxide-nitride-oxide (ONO) layer (34, 36, 38), formed on a substrate (30). A recess (44) is created through the ONO layer (32) and in the substrate (30). A metal silicide bit line (48) is formed in the recess (44) and bit line oxide (54) is formed on top of the metal silicide. A word line (56) is formed over the ONO layer (32) and the bit line oxide (54), and a low resistance silicide (58) is provided on top of the word line (56). The silicide (58) is formed by laser thermal annealing, for example.
摘要翻译：用于制造该器件的MONOS器件和方法具有形成在衬底（30）上的电荷捕获介电层（32），例如氧化物 - 氮化物 - 氧化物（ONO）层（34,36,38）。通过ONO层（32）和衬底（30）产生凹陷（44）。金属硅化物位线（48）形成在凹槽（44）中，位线氧化物（54）形成在金属硅化物的顶部。在ONO层（32）和位线氧化物（54）之上形成字线（56），并且在字线（56）的顶部设置低电阻硅化物（58）。硅化物（58）例如由激光热退火形成。

2. 发明申请

WO2004038804A3 SEMICONDUCTOR DEVICE HAVING A U-SHAPED GATE STRUCTURE 审中-公开
公开(公告)号：WO2004038804A3
公开(公告)日：2004-05-06
申请号：PCT/US2003/032663
申请日：2003-10-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： YU, Bin , AHMED, Shibly, S. , AN, Judy, Xilin , DAKSHINA-MURTHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong
IPC分类号： H01L29/423
摘要： A double-gate semiconductor device (100) includes a substrate (110), an insulating layer (120), a fin (210) and agate (510). The insulating layer (120) is formed on the substrate (110) and the gate (510) is formed on the insulating layer (120). The fin (210) has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin (210) are surrounded by the gate (510). The gate material (510) surrounding the fin (210) has a U-shaped cross-section at a channel region of the semiconductor device (100).

3. 发明申请

WO2010011287A1 METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION 审中-公开
标题翻译：形成具有热分解的微结构半导体器件的方法
公开(公告)号：WO2010011287A1
公开(公告)日：2010-01-28
申请号：PCT/US2009/004211
申请日：2009-07-21
申请人： ADVANCED MICRO DEVICES, INC. , LIN, Ming-ren , KRIVOKAPIC, Zoran , MASZARA, Witek
发明人： LIN, Ming-ren , KRIVOKAPIC, Zoran , MASZARA, Witek
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/76232 , H01L29/66795 , H01L29/66818 , H01L29/7851
摘要： A method of manufacturing a semiconductor device structure (300), such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material (302), a first conductive fin structure (306) formed from the bulk semiconductor material (302), and a second conductive fin structure (308) formed from the bulk semiconductor material (302). The first conductive fin structure (306) and the second conductive fin structure (308) are separated by a gap (322). Next, spacers (332, 334) are formed in the gap (322) and adjacent to the first conductive fin structure (306) and the second conductive fin structure (308). Thereafter, an etching step etches the bulk semiconductor material (302), using the spacers (332, 334) as an etch mask, to form an isolation trench (336) in the bulk semiconductor material (302). A dielectric material (340) is formed in the isolation trench (336), over the spacers (332, 334), over the first conductive fin structure (306), and over the second conductive fin structure (308). Thereafter, at least a portion of the dielectric material (340) and at least a portion of the spacers (332, 334) are etched away to expose an upper section (342) of the first conductive fin structure (306) and an upper section (342) of the second conductive fin structure (308), while preserving the dielectric material (340) in the isolation trench (336). Following these steps, the fabrication of the devices is completed in a conventional manner.
摘要翻译：提供了一种制造诸如FinFET器件结构的半导体器件结构（300）的方法。该方法开始于提供包括体半导体材料（302），由本体半导体材料（302）形成的第一导电鳍结构（306）和由本体半导体材料形成的第二导电鳍结构（308）的衬底 302）。第一导电翅片结构（306）和第二导电翅片结构（308）由间隙（322）分开。接下来，间隙（332,334）形成在间隙（322）中并与第一导电翅片结构（306）和第二导电翅片结构（308）相邻。此后，使用间隔物（332,334）作为蚀刻掩模，蚀刻步骤蚀刻体半导体材料（302），以在体半导体材料（302）中形成隔离沟槽（336）。绝缘材料（340）在隔离沟槽（336）中，在间隔物（332,334）之上，在第一导电鳍结构（306）之上，并在第二导电鳍结构（308）之上形成。此后，介电材料（340）的至少一部分和至少一部分间隔物（332,334）被蚀刻掉以暴露第一导电鳍结构（306）的上部分（342）和上部分（336）的绝缘材料（340），同时保持隔离沟槽（336）中的电介质材料（340）。按照这些步骤，以常规方式完成装置的制造。

4. 发明申请

WO2005048339A1 SELF ALIGNED DAMASCENE GATE 审中-公开
标题翻译：自对准丹麦门
公开(公告)号：WO2005048339A1
公开(公告)日：2005-05-26
申请号：PCT/US2004/033251
申请日：2004-10-08
申请人： ADVANCED MICRO DEVICES, INC. , TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
发明人： TABERY, Cyrus, E. , AHMED, Shibly, S. , BUYNOSKI, Matthew, S. , DAKSHINA-MURPHY, Srikanteswara , KRIVOKAPIC, Zoran , WANG, Haihong , YANG, Chih-Yuh , YU, Bin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320) to expose a channel area (330) of the MOSFET (200), etching the fin (310) to thin a width of the fin (310) in the channel area (330), forming a gate over the fin (310), and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种用于形成金属氧化物半导体场效应晶体管（200）的方法，包括在衬底上形成翅片区域，源极区域和漏极区域，在翅片区域形成翅片（310），并形成在翅片区域中的掩模（320）。该方法还包括蚀刻掩模（320）以暴露MOSFET（200）的沟道区域（330），蚀刻鳍片（310）以使沟槽区域（330）中的鳍片（310）的宽度变薄，从而形成在所述翅片（310）上方的栅极，以及形成与所述栅极，所述源极区域和所述漏极区域的接触。

5. 发明申请

WO2004068585A1 STRAINED CHANNEL FINFET 审中-公开
标题翻译：应变通道FINFET
公开(公告)号：WO2004068585A1
公开(公告)日：2004-08-12
申请号：PCT/US2004/000967
申请日：2004-01-15
申请人： ADVANCED MICRO DEVICES, INC. , DAKSHINA-MURTHY, Srikanteswara , AN, Judy, Xilin , KRIVOKAPIC, Zoran , WANG, Haihong , YU, Bin
发明人： DAKSHINA-MURTHY, Srikanteswara , AN, Judy, Xilin , KRIVOKAPIC, Zoran , WANG, Haihong , YU, Bin
IPC分类号： H01L29/10
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/4908 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A semiconductor structure includes a fin (205) and a layer (305) formed on the fin. The fin (205) includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer (305) is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the layer (305).
摘要翻译：半导体结构包括翅片（205）和形成在翅片上的层（305）。翅片（205）包括具有矩形横截面和多个表面的第一晶体材料。层（305）形成在表面上并且包括第二结晶材料。第一结晶材料具有与第二结晶材料不同的晶格常数，以在层（305）内引起拉伸应变。

6. 发明申请

WO2002061801A2 DUAL GATE PROCESS USING SELF-ASSEMBLED MOLECULAR LAYER 审中-公开
标题翻译：使用自组装分子层的双门过程
公开(公告)号：WO2002061801A2
公开(公告)日：2002-08-08
申请号：PCT/US2001/048594
申请日：2001-12-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KRIVOKAPIC, Zoran
IPC分类号： H01L
CPC分类号： B82Y30/00 , B82Y10/00 , H01L21/32139 , H01L21/823842
摘要： A method of forming dual gate structures on first (40) and second portions (42) of a substrate (38) includes: providing an insulative layer (52) over the substrate (38); providing a first layer of material (54) having a first work function over the first portion (40) of the substrate (38); providing a second layer of material (62) having a second work function different than the first work function over the second portion (42) of the substrate (38); patterning a third layer of material (70) over the first (54) and second layers (62) of material, whereby features of the third layer of material (70) are provided over both the first and second portions (40, 42) of the substrate (38); providing a self-assembled molecular layer (76) over at least a portion of the features, wherein the self-assembled molecular layer (76) has regions of etch selectivity (78, 80); and etching the self-assembled molecular layer (76) at the regions of etch selectivity (78, 80) until gate structures (22, 24) are formed over the first (40) and second portions (42) of the substrate (38).
摘要翻译：在衬底（38）的第一（40）和第二部分（42）上形成双栅极结构的方法包括：在衬底（38）上方提供绝缘层（52）; 在衬底（38）的第一部分（40）上提供具有第一功函数的第一层材料（54）; 在所述基板（38）的第二部分（42）上提供具有与所述第一功函数不同的第二功函数的第二层材料（62）; 在材料的第一（54）和第二层（62）上图案化第三层材料（70），由此第三层材料（70）的特征设置在第一和第二部分（40,42）两者之上，基板（38）; 在所述特征的至少一部分上提供自组装分子层（76），其中所述自组装分子层（76）具有蚀刻选择性区域（78,80）; 以及在蚀刻选择性（78,80）的区域蚀刻自组装分子层（76），直到在衬底（38）的第一部分（40）和第二部分（42）上形成栅极结构（22,24）。

7. 发明申请

WO2006052379A1 STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：绝缘子半导体器件上的全绝缘硅及其制造方法
公开(公告)号：WO2006052379A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/036894
申请日：2005-10-12
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , SUBBA, Niraj , MASZARA, Witold, P. , KRIVOKAPIC, Zoran , LIN, Ming-Ren
发明人： XIANG, Qi , SUBBA, Niraj , MASZARA, Witold, P. , KRIVOKAPIC, Zoran , LIN, Ming-Ren
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconductor layer (106). A spacer (304) is formed around the gate (204), and the semiconductor layer (106) and the insulator (104) are removed outside the spacer (304). Recessed source/drain (402) are formed outside the spacer (304).
摘要翻译：提供了一种半导体衬底（102），其上具有绝缘体（104），绝缘体（104）上具有半导体层（106）。形成深沟槽隔离（108），将应变引入半导体层（106）。在半导体层（106）上形成栅极电介质（202）和栅极（204）。在栅极（204）周围形成间隔物（304），并且将半导体层（106）和绝缘体（104）去除在间隔物304的外部。嵌入式源极/漏极（402）形成在间隔物（304）的外侧。

8. 发明申请

WO2004068589A1 NARROW FIN FINFET 审中-公开
公开(公告)号：WO2004068589A1
公开(公告)日：2004-08-12
申请号：PCT/US2004/000963
申请日：2004-01-15
申请人： ADVANCED MICRO DEVICES, INC. , KRIVOKAPIC, Zoran , AN, Judy, Xilin , DAKSHINA-MURTHY, Srikanteswara , WANG, Haihong , YU, Bin
发明人： KRIVOKAPIC, Zoran , AN, Judy, Xilin , DAKSHINA-MURTHY, Srikanteswara , WANG, Haihong , YU, Bin
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66818 , H01L29/78687
摘要： A narrow channel FinFET is described herein with a channel width of less than 6 nm. The FinFET may include a fin (140) in which the channel area is trimmed using a NH 4 OH etch or a reactive ion etch (RIE).
摘要翻译：本文描述了窄通道FinFET，其通道宽度小于6nm。 FinFET可以包括翅片（140），其中使用NH 4 OH蚀刻或反应离子蚀刻（RIE）来修整沟道区域。

9. 发明申请

WO2002101819A2 LEAKY, THERMALLY CONDUCTIVE INSULATOR MATERIAL (LTCIM) IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE 审中-公开
标题翻译：半导体绝缘体（SOI）结构中的漏电导热绝缘材料（LTCIM）
公开(公告)号：WO2002101819A2
公开(公告)日：2002-12-19
申请号：PCT/US2002/002991
申请日：2002-01-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： JU, Dong-Hyuk , EN, William, George , KRISHNAN, Srinath , RICCOBENE, Concetta, E. , KRIVOKAPIC, Zoran , AN, Judy, Xilin , YU, Bin
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/187 , H01L29/78603 , H01L29/78606 , H01L29/78609 , H01L29/78612
摘要： A device and method for making a semiconductor-on-insulator (SOI) structure (10) having a leaky, thermally conductive material (LTCIM) layer (14) disposed between a semiconductor substrate (12) and a semiconductor layer (13).
摘要翻译：一种用于制造绝缘体上半导体（SOI）结构（10）的装置和方法，其具有设置在半导体衬底（12）和半导体层（13）之间的泄漏的导热材料（LTCIM）层（14）。

10. 发明申请

WO2005001908A2 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005001908A2
公开(公告)日：2005-01-06
申请号：PCT/US2004/017727
申请日：2004-06-05
申请人： ADVANCED MICRO DEVICES, INC. , KRIVOKAPIC, Zoran
发明人： KRIVOKAPIC, Zoran
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A strained semiconductor device suitable for use in an integrated circuit and a method for manufacturing the strained semiconductor device. A mesa isolation structure is formed from a semiconductor on-insulator substrate. A gate structure is formed on the mesa isolation structure. The gate structure includes a gate disposed on a gate dielectric material and has two sets of opposing sidewalls. Semiconductor material is selectively grown on portions of the mesa isolation structure adjacent a first set of opposing sidewalls of the gate structure and then doped. The doped semiconductor material is silicided and protected by a dielectric material. The gate is silicided wherein the silicide wraps around a second set of opposing sidewalls and stresses a channel region of the semiconductor device.
摘要翻译：适用于集成电路的应变半导体器件和制造应变半导体器件的方法。由绝缘体上半导体基板形成台面隔离结构。在台面隔离结构上形成栅极结构。栅极结构包括设置在栅极电介质材料上并具有两组相对侧壁的栅极。半导体材料选择性地生长在邻近栅极结构的第一组相对侧壁的台面隔离结构的部分上，然后掺杂。掺杂的半导体材料被电介质材料硅化并保护。栅极是硅化物，其中硅化物围绕第二组相对的侧壁缠绕并且强迫半导体器件的沟道区域。

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