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1. 发明申请

WO2002082503A2 MULTI-THICKNESS SILICIDE DEVICE 审中-公开
标题翻译：多层硅化物装置
公开(公告)号：WO2002082503A2
公开(公告)日：2002-10-17
申请号：PCT/US2001/049829
申请日：2001-12-19
申请人： ADVANCED MICRO DEVICES, INC.
发明人： EN, William, G. , KRISHNAN, Srinath , JU, Dong-Hyuk , YU, Bin
IPC分类号： H01L
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/41733 , H01L29/458 , H01L29/6653 , H01L29/6656 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： A transistor device (10) formed on a semiconductor substrate (12) with an active layer (13) disposed on the semiconductor substrate having active regions (18) defined by isolation trenches (16). The device includes a gate (36) defining a channel (20) interposed between a source and a drain (22) formed within the active region of the substrate. Further, the device includes a multi-thickness silicide layer (42 and 44) formed on the main source and drain regions (24 and 26) and source and drain extension regions (28 and 30) wherein a portion (54) of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion (46) of the silicide layer which is formed on the mainn source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate. Further still, the device includes a disposable spacer used in the formation of the device. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.
摘要翻译：一种晶体管器件（10），其形成在半导体衬底（12）上，其中有源层（13）设置在半导体衬底上，该有源层具有由隔离沟槽（16）限定的有源区（18）。该装置包括限定了在衬底的有源区域内形成的源极和漏极之间的沟道（20）的栅极（36）。此外，器件包括形成在主源极和漏极区域（24和26）以及源极和漏极延伸区域（28和30）上的多层硅化物层（42和44），其中，形成在源极和漏极延伸区域上的厚度硅化物层比形成在主要源极和漏极区域上的硅化物层的部分（46）薄。该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。此外，该装置还包括用于形成装置的一次性间隔件。此外，该器件包括形成在源极和漏极上的多个薄硅化物层。另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。此外，该装置还包括用于形成装置的多个间隔物。该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

2. 发明申请

WO2002101819A2 LEAKY, THERMALLY CONDUCTIVE INSULATOR MATERIAL (LTCIM) IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE 审中-公开
标题翻译：半导体绝缘体（SOI）结构中的漏电导热绝缘材料（LTCIM）
公开(公告)号：WO2002101819A2
公开(公告)日：2002-12-19
申请号：PCT/US2002/002991
申请日：2002-01-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： JU, Dong-Hyuk , EN, William, George , KRISHNAN, Srinath , RICCOBENE, Concetta, E. , KRIVOKAPIC, Zoran , AN, Judy, Xilin , YU, Bin
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/187 , H01L29/78603 , H01L29/78606 , H01L29/78609 , H01L29/78612
摘要： A device and method for making a semiconductor-on-insulator (SOI) structure (10) having a leaky, thermally conductive material (LTCIM) layer (14) disposed between a semiconductor substrate (12) and a semiconductor layer (13).
摘要翻译：一种用于制造绝缘体上半导体（SOI）结构（10）的装置和方法，其具有设置在半导体衬底（12）和半导体层（13）之间的泄漏的导热材料（LTCIM）层（14）。

3. 发明申请

WO2003052799A2 A METHOD OF FORMING DIFFERENTIAL SPACERS FOR INDIVIDUAL OPTIMIZATION OF N-CHANNEL AND P-CHANNEL TRANSISTORS 审中-公开
标题翻译：形成N沟道和P沟道晶体管的个性优化的差分空间的方法
公开(公告)号：WO2003052799A2
公开(公告)日：2003-06-26
申请号：PCT/US2002/039782
申请日：2002-12-11
申请人： ADVANCED MICRO DEVICES, INC.
发明人： JU, Dong-Hyuk
IPC分类号： H01L21/00
CPC分类号： H01L21/823814 , H01L21/823864
摘要： A method of forming a semiconductor with n-channel (12) and p-channel transistors (14) with optimum gate to drain overlap capacitances for each of the different types of transistors, uses differential spacing on gate electrodes (16) for the respective transistors (12, 14). A first offset spacer (18) is formed on the gate electrode (16) and an n-channel extension implant is performed to create source/drain extensions (20) for the n-channel transistors (12) spaced an optimum distance away from the gate electrodes (16). Second offset spacers (22) are formed on the first offset spacers (18), and a p-channel source/drain extension implant is formed to create source/drain extensions (26) for the p-channel transistors (14). The increased spacing of the source/drain extension implants (26) away from the gate electrodes (16) in the p-channel transistors (14) accounts for the faster diffusion of the p-type dopants in comparison to the n-type dopants.
摘要翻译：用于对于不同类型的晶体管中的每一个，以n沟道（12）和p沟道晶体管（14）形成具有最佳栅极 - 漏极重叠电容的半导体的方法使用用于各个晶体管的栅电极（16）上的差分间隔（12,14）。第一偏移间隔物（18）形成在栅电极（16）上，并且执行n沟道延伸注入以产生用于n沟道晶体管（12）的源极/漏极延伸部（20），间隔开距离栅电极（16）。第二偏移间隔物（22）形成在第一偏移间隔物（18）上，并且形成p沟道源极/漏极延伸注入以产生用于p沟道晶体管（14）的源极/漏极延伸部（26）。与p型晶体管（14）中的栅极电极（16）之间的源极/漏极延伸植入物（26）的间隔增加，与p型掺杂剂相比，n型掺杂剂的扩散更快。

4. 发明申请

WO2002061841A2 SALICIDE BLOCKED DIODE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：杀菌剂封闭二极管及其制造方法
公开(公告)号：WO2002061841A2
公开(公告)日：2002-08-08
申请号：PCT/US2001/047113
申请日：2001-12-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BEEBE, Stephen, G. , JU, Dong-Hyuk , EN, William, G.
IPC分类号： H01L29/00
CPC分类号： H01L29/417 , H01L27/0255 , H01L27/1203 , H01L29/861
摘要： A silicon-on-insulator (SOI) diode (10). The SOI diode (10) has an active region (18) having an anode (20) disposed adjacent a cathode (22); a first silicide layer (24) formed on the anode (20) distal a junction between the anode (20) and the cathode (22) and a second silicide layer (24) formed on the cathode (22) distal the the junction between the anode (20) and the cathode (22); and an oxide layer (26) isolating the first and second silicide layers (24). Also disclosed is a method of fabricating the SOI diode (10).
摘要翻译：绝缘体上硅（SOI）二极管（10）具有邻近阴极（22）设置有阳极（20）的有源区（18）。在阳极（20）和阴极（22）之间的接合部分的远端形成在阳极（20）上的第一硅化物层（24）和形成在阴极（22）上的第二硅化物层（24）阳极（20）和阴极（22）; 和隔离第一和第二硅化物层（24）的氧化物层（26）。还公开了制造SOI二极管（10）的方法。

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