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1. 发明申请

WO2009064660A1 BIT PATTERNED MAGNETIC MEDIA DATA FORMAT 审中-公开
标题翻译：位图形磁介质数据格式
公开(公告)号：WO2009064660A1
公开(公告)日：2009-05-22
申请号：PCT/US2008/082686
申请日：2008-11-06
申请人： MARVELL WORLD TRADE LTD , YANG, Xueshi
发明人： YANG, Xueshi
IPC分类号： G11B20/12 , G11B20/14 , G11B5/596 , G11B5/855
CPC分类号： G11B20/1403 , G11B5/59655 , G11B5/855 , G11B20/10222 , G11B20/1217 , G11B2020/1232 , G11B2020/1287 , G11B2020/1298 , G11B2020/1836 , G11B2220/2516
摘要： In an implementation, a media drive (102) comprises bit patterned magnetic media (104) and one or more modules (108, 110, 112, 114). The one or more modules are to cause data (202) to be written on the bit patterned magnetic media (104) in a data sector (106) that includes a synchronization mark (116) disposed between data blocks (118, 120) of the data sector (106).
摘要翻译：在一个实现中，介质驱动器（102）包括位图案磁介质（104）和一个或多个模块（108,110,112,114）。一个或多个模块将使数据（202）被写入数据扇区（106）中的位图案磁介质（104）上，数据扇区（106）包括设置在该数据块（118,120）之间的同步标记（116）数据扇区（106）。

2. 发明申请

WO2008045292A3 ERROR CORRECTION DECODING METHODS AND APPARATUS 审中-公开
标题翻译：错误修正方法和设备
公开(公告)号：WO2008045292A3
公开(公告)日：2008-07-03
申请号：PCT/US2007021333
申请日：2007-10-04
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , WU ZINING , TANG HENG
发明人： YANG XUESHI , WU ZINING , TANG HENG
IPC分类号： H04L1/00 , H03M13/29
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/293 , H04L1/0065
摘要： A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.
摘要翻译：用于纠错解码的方法和系统使用连接的纠错解码器。信道解码器从传输信道接收编码用户数据，对用户数据的比特进行解码，并生成解码比特的擦除信息。解码的比特和擦除信息由外部ECC解码器接收，该外部ECC解码器首先执行擦除解码。如果擦除解码成功，则输出解码的用户数据。如果擦除解码不成功，则外部ECC解码器执行更复杂的错误解码。因此，不需要对可以使用擦除解码成功解码的用户数据执行错误解码。避免执行错误解码所需的额外操作。以这种方式，减少整体解码过程的复杂性，显着降低所需的计算能力，同时保持所需的性能水平。

3. 发明申请

WO2008045893A1 ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS 审中-公开
标题翻译：用于存储和从存储器存储数据的自适应系统和方法
公开(公告)号：WO2008045893A1
公开(公告)日：2008-04-17
申请号：PCT/US2007/080845
申请日：2007-10-09
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining
发明人： YANG, Xueshi , WU, Zining
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block may be configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block may be configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.
摘要翻译：这里描述了可能有助于确保从存储器单元检索的数据的可靠性的自适应系统和方法。系统可以包括包括多个存储器单元，数据质量监控块和自适应数据编码块的存储器件，数据质量监控块和自适应数据编码块都可操作地耦合到存储器件。数据质量监测块可以被配置为确定存储器件中包括的一个或多个存储器单元的组的质量值，所确定的质量值指示一个或多个存储器单元的组的质量。自适应数据编码块可以被配置为从多个编码方案中选择编码方案来编码要写入存储器件中的一个或多个存储器单元的组的数据，编码方案的选择至少基于部分是确定的一个或多个存储单元的组的质量值。

4. 发明申请

WO2012106255A1 MAPPING DATA TO NON-VOLATILE MEMORY 审中-公开
标题翻译：将数据映射到非易失性存储器
公开(公告)号：WO2012106255A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023165
申请日：2012-01-30
申请人： MARVELL WORLD TRADE LTD. , CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
发明人： CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure that includes a plurality of multi- level memory cells. The described system includes a controller configured to map a data segment to the plurality of multi -level memory cells. A first portion of a first set of consecutive bits of a data segment (sector 1) is mapped to a first page (LSBpage) associated with the plurality of multi -level memory cells. A second portion of the first set of consecutive bits of the data segment (sectorl) is mapped to a second page (MSB page) associated with the plurality of multi -level memory cells. A first portion of a second set of consecutive bits of the data segment (sector2) is mapped to the first page. A second portion of the second set of consecutive bits of the data segment is mapped to the second page. The first page is associated with bits of a first significance (LSB), and the second page is associated with bits of a second significance (MSB).
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括包括多个多级存储器单元的非易失性存储器结构。所描述的系统包括被配置为将数据段映射到多个多层存储器单元的控制器。数据段（扇区1）的第一组连续位的第一部分被映射到与多个多层存储器单元相关联的第一页（LSB页）。数据段（扇区1）的第一组连续位的第二部分被映射到与多个多层存储器单元相关联的第二页（MSB页）。数据段（扇区2）的第二组连续位的第一部分被映射到第一页。数据段的第二组连续位的第二部分被映射到第二页。第一页与第一有效位（LSB）的位相关联，并且第二页与第二有效位（MSB）的位相关联。

5. 发明申请

WO2008058082A2 ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS 审中-公开
标题翻译：用于记忆细胞的自适应读取和写入系统和方法
公开(公告)号：WO2008058082A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/083649
申请日：2007-11-05
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , BURD, Gregory
发明人： YANG, Xueshi , BURD, Gregory
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Adaptive memory read and write systems and methods are described herein that adapts to changes to threshold voltage distributions of memory cells as of result of, for example, the detrimental affects of repeated cycling operations of the memory cells. The novel systems may include at least multi-level memory cells, which may be multi-level flash memory cells, and a computation block operatively coupled to the multi-level memory cells. The computation block may be configured to compute optimal or near optimal mean and detection threshold values based, at least in part, on estimated mean and standard deviation values of level distributions of the multi-level memory cells. The optimal or near optimal mean and detection threshold values computed by the computation block may be subsequently used to facilitate writing and reading, respectively, of data to and from the multi-level memory cells.
摘要翻译：本文描述了自适应存储器读写系统和方法，其适应于存储器单元的阈值电压分布的变化，例如由于存储器单元的重复循环操作的有害影响。该新颖系统可以包括至少多级存储器单元，其可以是多级闪存单元，以及可操作地耦合到多级存储器单元的计算块。该计算块可以被配置为至少部分地基于多级存储器单元的级别分布的估计平均值和标准偏差值来计算最佳或近似最优的平均值和检测阈值。随后可以使用由计算块计算的最佳或接近最优的平均值和检测阈值，以便于分别向多层存储器单元写入和读取数据。

6. 发明申请

WO2012154255A1 RELIABILITY METRICS MANAGEMENT FOR SOFT DECODING 审中-公开
标题翻译：软解码的可靠性量度管理
公开(公告)号：WO2012154255A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/025482
申请日：2012-02-16
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi
发明人： YANG, Xueshi
IPC分类号： G06F11/10
CPC分类号： G11C16/28 , G06F11/1048 , G11C16/26 , G11C29/00
摘要： Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector.
摘要翻译：实施例提供了一种用于读取存储器的目标存储器扇区的方法。该方法包括：基于对应于存储器的多个存储器扇区的读取数据，估计第一个一个或多个参考电压，并且使用第一个一个或多个参考电压对目标存储器扇区执行第一读取操作。该方法还包括确定第一读取操作的纠错码（ECC）解码失败，并且响应于确定第一读取操作的ECC解码失败并且基于对应于目标存储器扇区的读取数据，更新估计第一个或多个参考电压以产生第二个一个或多个参考电压。该方法还包括使用第二个一个或多个参考电压，对目标存储器扇区执行第二读取操作。

7. 发明申请

WO2009021065A1 ENCODING AND DECODING USING GENERALIZED CONCATENATED CODES (GCC) 审中-公开
标题翻译：使用通用的编码（GCC）编码和解码
公开(公告)号：WO2009021065A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/072373
申请日：2008-08-06
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , BURD, Gregory , TANG, Heng , CHAICHANAVONG, Panu , WU, Zining
发明人： YANG, Xueshi , BURD, Gregory , TANG, Heng , CHAICHANAVONG, Panu , WU, Zining
IPC分类号： H03M13/29
CPC分类号： H03M13/2945 , G06F11/1068 , H03M13/033 , H03M13/1515 , H03M13/2903 , H03M13/2906
摘要： Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. Hence, the number of outer codes is reduced by replacing the last layer (s) of outer code (s) by uncoded symbols. The GCC codes may be concatenated with an outer-layer code or an inner-layer code.
摘要翻译：描述使用广义级联码（GCC）的编码和解码的系统，装置和方法。方法包括接收数据; 对所接收的数据进行编码以获得第一编码数据; 对第一编码数据进行编码，直到GCC编码达到中间级; 并终止中级的GCC编码。因此，通过用未编码的符号代替外部码的最后一层来减少外部码的数量。 GCC代码可以与外层代码或内层代码连接。

8. 发明申请

WO2009105153A1 SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION 审中-公开
标题翻译：用于执行定向错误校正的系统和方法
公开(公告)号：WO2009105153A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/000632
申请日：2009-01-30
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , LOW, Seo-how
发明人： YANG, Xueshi , WU, Zining , LOW, Seo-how
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1072 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
摘要翻译：提供了一种用于执行串联纠错的系统和方法。在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有第一个逻辑单元。该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

9. 发明申请

WO2009075918A1 SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE 审中-公开
标题翻译：具有细胞间干扰的闪存的序列检测
公开(公告)号：WO2009075918A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/074414
申请日：2008-08-27
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining
发明人： YANG, Xueshi , WU, Zining
IPC分类号： G11C7/02 , G11C7/10
CPC分类号： G11C16/04 , G11C7/02 , G11C7/14 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C16/3422
摘要： A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.
摘要翻译：存储器集成电路（IC）包括读取模块和序列检测器模块。读取模块读取沿着位线和字线中的一个位置的S个存储单元（单元），并产生S个读取信号，其中S是大于1的整数。序列检测器模块基于S个读取信号来检测数据序列和参考信号。数据序列包括存储在S单元中的数据。每个参考信号包括与S个小区中的一个相关联的无干扰信号和与S个小区之一相邻的S个小区中的另一个的干扰信号。

10. 发明申请

WO2008100529A3 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的导引放置
公开(公告)号：WO2008100529A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , WU ZINING , SUTARDJA PANTAS
发明人： YANG XUESHI , WU ZINING , SUTARDJA PANTAS
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括格式化模块，该格式化模块与包括B个存储器块的存储器阵列通信，每个B存储器块包括P个物理页面和Q个逻辑页面。格式模块选择X个预定位置以在每个B存储块中写入导频数据和回读导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与回读的导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

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