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1. 发明申请

WO2008045292A3 ERROR CORRECTION DECODING METHODS AND APPARATUS 审中-公开
标题翻译：错误修正方法和设备
公开(公告)号：WO2008045292A3
公开(公告)日：2008-07-03
申请号：PCT/US2007021333
申请日：2007-10-04
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , WU ZINING , TANG HENG
发明人： YANG XUESHI , WU ZINING , TANG HENG
IPC分类号： H04L1/00 , H03M13/29
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/293 , H04L1/0065
摘要： A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.
摘要翻译：用于纠错解码的方法和系统使用连接的纠错解码器。信道解码器从传输信道接收编码用户数据，对用户数据的比特进行解码，并生成解码比特的擦除信息。解码的比特和擦除信息由外部ECC解码器接收，该外部ECC解码器首先执行擦除解码。如果擦除解码成功，则输出解码的用户数据。如果擦除解码不成功，则外部ECC解码器执行更复杂的错误解码。因此，不需要对可以使用擦除解码成功解码的用户数据执行错误解码。避免执行错误解码所需的额外操作。以这种方式，减少整体解码过程的复杂性，显着降低所需的计算能力，同时保持所需的性能水平。

2. 发明申请

WO2008100529A3 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的导引放置
公开(公告)号：WO2008100529A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , WU ZINING , SUTARDJA PANTAS
发明人： YANG XUESHI , WU ZINING , SUTARDJA PANTAS
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括格式化模块，该格式化模块与包括B个存储器块的存储器阵列通信，每个B存储器块包括P个物理页面和Q个逻辑页面。格式模块选择X个预定位置以在每个B存储块中写入导频数据和回读导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与回读的导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

3. 发明申请

WO2010141650A3 REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY 审中-公开
标题翻译： FLASH存储器参考电压优化
公开(公告)号：WO2010141650A3
公开(公告)日：2011-08-11
申请号：PCT/US2010037155
申请日：2010-06-03
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI
发明人： YANG XUESHI
IPC分类号： G11C16/26 , G11C16/30
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/30 , H01L27/115
摘要： A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.
摘要翻译：系统包括电压发生器和参考电压设定模块。电压发生器被配置为产生要施加到存储器单元的K电压。 K电压用于确定用于读取存储器单元的参考电压，其中K是大于1的整数。参考电压设置模块被配置为选择性地将参考电压设置为K个电压中的两个相邻电压之间的值或K个电压中的两个相邻的电压之一。

4. 发明申请

WO2008058082A3 ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS 审中-公开
标题翻译：记忆细胞的自适应读写系统和方法
公开(公告)号：WO2008058082A3
公开(公告)日：2008-09-12
申请号：PCT/US2007083649
申请日：2007-11-05
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , BURD GREGORY
发明人： YANG XUESHI , BURD GREGORY
IPC分类号： G11C16/28 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Adaptive memory read and write systems and methods are described herein that adapts to changes to threshold voltage distributions of memory cells as of result of, for example, the detrimental affects of repeated cycling operations of the memory cells. The novel systems may include at least multi-level memory cells, which may be multi-level flash memory cells, and a computation block operatively coupled to the multi-level memory cells. The computation block may be configured to compute optimal or near optimal mean and detection threshold values based, at least in part, on estimated mean and standard deviation values of level distributions of the multi-level memory cells. The optimal or near optimal mean and detection threshold values computed by the computation block may be subsequently used to facilitate writing and reading, respectively, of data to and from the multi-level memory cells.
摘要翻译：本文描述了自适应存储器读取和写入系统和方法，其适应于由于例如存储器单元的重复循环操作的不利影响而导致的存储器单元的阈值电压分布的改变。新颖的系统可以至少包括多级存储单元，其可以是多级闪存单元，以及可操作地耦合到多级存储单元的计算块。计算块可以被配置为至少部分地基于多级存储器单元的电平分布的估计平均值和标准偏差值来计算最佳或接近最佳平均值和检测阈值。随后可以使用由计算块计算的最佳或接近最佳的平均值和检测阈值来分别便于写入和读取来自多级存储器单元的数据以及从多级存储器单元读取数据。

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