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1. 发明申请

WO2009009420A2 LOW GLITCH OFFSET CORRECTION CIRCUIT FOR AUTO-ZERO SENSOR AMPLIFIERS AND METHOD 审中-公开
标题翻译：用于自动零点传感器放大器的低灵敏度偏移校正电路和方法
公开(公告)号：WO2009009420A2
公开(公告)日：2009-01-15
申请号：PCT/US2008/069157
申请日：2008-07-03
申请人： TEXAS INSTRUMENTS INCORPORATED , TRIFONOV, Dimitar, T. , LARSON, Tony, R. , DOORENBOS, Jerry, L.
发明人： TRIFONOV, Dimitar, T. , LARSON, Tony, R. , DOORENBOS, Jerry, L.
IPC分类号： H03F3/45 , G01R1/30
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (HA) and second (12A) input amplifiers having outputs (15A, B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFLX a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFHX a second input signal (Vin ) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).
摘要翻译：仪表放大器包括具有耦合到输出放大器（13）的输出（15A，B）的第一（HA）和第二（12A）输入放大器。第一输入放大器中的第一自动调零阶段（20）被自动调零至第一电压电平（VREFLX），第一输入放大器中的第二自动调零阶段（24）放大第一输入信号（Vin +），并且放大的第一输入信号在第一阶段（A）期间耦合到输出放大器。第二输入放大器中的第三自动调零阶段（44）被自动调零到第二电压电平（VREFHX），第二输入信号（Vin）由第二输入放大器中的第四自动调零级（40）放大，并且放大的第二输入信号在第二阶段（B）期间耦合到输出放大器。第二自动调零阶段是自动调零阶段在第三阶段（C）期间，第一自动调零阶段（20）放大第一输入信号，并且放大后的第一输入信号耦合到输出放大器，零级被自动归零到第二电压电平，第二输入信号被第三自动归零站放大 ge，并且放大的第二输入信号在第四阶段（D）期间耦合到输出放大器。

2. 发明申请

WO2008055139A3 DIGITAL-TO-ANALOG CONVERTER ARCHITECTURE AND METHOD HAVING LOW SWITCH COUNT AND SMALL OUTPUT IMPEDANCE 审中-公开
标题翻译：具有低开关次数和小输出阻抗的数字 - 模拟转换器结构和方法
公开(公告)号：WO2008055139A3
公开(公告)日：2008-11-06
申请号：PCT/US2007082970
申请日：2007-10-30
申请人： TEXAS INSTRUMENTS INC , TRIFONOV DIMITAR T , DOORENBOS JERRY L
发明人： TRIFONOV DIMITAR T , DOORENBOS JERRY L
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765 , H03M1/785
摘要： A digital-to-analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (VO) to produce coarse resolution node voltages (V0,...V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,l...) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Voutl), the second output voltage (Voutl) and the first output voltage (Vout2) providing a differential analog output signal (Voutl -Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R- 2R networks.
摘要翻译：数模转换器包括耦合在第一电压（Vin）和中间电压（VO）之间以产生粗分辨率节点电压（V0，... V240）的粗分辨率电阻器电路（11），并且还包括高分辨率电阻电路（20），耦合在中间电压和第二电压（GND）之间。响应于数字输入（D0，I ...）的一组MSB位选择粗分辨率节点电压之一以产生第一输出电压（Vout2），并且选择其中一个精细分辨率节点电压响应于数字输入的一组LSB位以产生第二输出电压（Vout1），第二输出电压（Vout1）和提供差分模拟输出信号（Vout1-Vout2）的第一输出电压（Vout2）。在一个实施例中，粗分辨率和精细分辨率电阻器电路是串电阻器电路，并且在另一个实施例中，它们是修改的R-2R网络。

3. 发明申请

WO2007100406A3 REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION 审中-公开
标题翻译：减少PIN码扫描链实现
公开(公告)号：WO2007100406A3
公开(公告)日：2008-02-21
申请号：PCT/US2006061857
申请日：2006-12-11
申请人： TEXAS INSTRUMENTS INC , DOORENBOS JERRY L , TRIFONOV DIMITAR , GARDNER MARCO A
发明人： DOORENBOS JERRY L , TRIFONOV DIMITAR , GARDNER MARCO A
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/3172
摘要： A synchronous logic device with reduced pin count scan chain includes more than two flip/flops (SDCO, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataln), a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal, a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode, a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut).
摘要翻译：具有减少的引脚数扫描链的同步逻辑器件包括耦合以形成用于接收扫描数据输入信号（ScanDataln）的移位寄存器的多于两个的触发器（SDCO，SDC1，SDC2），用于接收的组合逻辑电路设备输入，为两个以上的触发器产生触发器输入，以及产生输出信号;第一多路复用器（MUX10），用于在测试模式期间向多于两个的触发器提供时钟信号;第二多路复用器（MUX12），用于在从移位寄存器输出的测试模式与来自组合逻辑电路（20）的输出信号之间进行选择，并提供扫描数据输出信号（ScanDataOut）。

4. 发明申请

WO2011126530A1 SEMICONDUCTOR THERMOCOUPLE AND SENSOR 审中-公开
标题翻译：半导体热电偶和传感器
公开(公告)号：WO2011126530A1
公开(公告)日：2011-10-13
申请号：PCT/US2010/062055
申请日：2010-12-23
申请人： TEXAS INSTRUMENTS INCORPORATED , TRIFONOV, Dimitar, T. , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： TRIFONOV, Dimitar, T.
IPC分类号： H01L35/32
CPC分类号： H01L23/38 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： "On-chip" or monolithically integrated thermocouples are provided that employ different thicknesses of thermal insulators to create thermal differentials within an integrated circuit. Heat applied to a metallization layer (334) is transferred through other metallization layers (328, 314- 1) and vias (330, 322, 310-1) to a conductive layer (306-1) having portions overlying a thick dielectric layer (field oxide layer 302) and a more thermally conductive thin oxide layer (304), forming a "hot" junction between a via (310-1) and the conductive layer (306-1), and a "cold" junction between the conductive layer (306-1) and another via (312-1), to generate a voltage.
摘要翻译：提供“片上”或单片集成热电偶，其采用不同厚度的绝热体，以在集成电路内产生热差。施加到金属化层（334）的热量通过其它金属化层（328,314-1）和通孔（330,322,310-1）转移到具有覆盖在厚电介质层上的部分的导电层（306-1）场氧化物层302）和更高导热的薄氧化物层（304），在通孔（310-1）和导电层（306-1）之间形成“热”结，以及导电层（306-1）和另一个通孔（312-1），以产生电压。

5. 发明申请

WO2009009420A3 LOW GLITCH OFFSET CORRECTION CIRCUIT FOR AUTO-ZERO SENSOR AMPLIFIERS AND METHOD 审中-公开
标题翻译：用于自动零点传感器放大器和方法的低电平偏移校正电路
公开(公告)号：WO2009009420A3
公开(公告)日：2009-04-16
申请号：PCT/US2008069157
申请日：2008-07-03
申请人： TEXAS INSTRUMENTS INC , TRIFONOV DIMITAR T , LARSON TONY R , DOORENBOS JERRY L
发明人： TRIFONOV DIMITAR T , LARSON TONY R , DOORENBOS JERRY L
IPC分类号： H03F3/45 , G01R1/30
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (HA) and second (12A) input amplifiers having outputs (15A, B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFLX a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFHX a second input signal (Vin ) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).
摘要翻译：仪表放大器包括具有耦合到输出放大器（13）的输出（15A，B）的第一（HA）和第二（12A）输入放大器。第一输入放大器中的第一自动调零级（20）自动归零为第一电压电平（VREFLX，第一输入信号（Vin +）被第一输入放大器中的第二自动调零级放大，并且放大的第一输入信号在第一相位（A）期间耦合到输出放大器，第二输入放大器中的第三自动归零级（44）自动归零到第二电压电平（VREFHX，第二输入信号（Vin）在第二输入放大器中由第四自动调零级（40）放大，并且放大的第二输入信号在第二阶段（B）期间耦合到输出放大器，第二自动归零级是自动的在第三阶段（C）期间，第一输入信号由第一自动调零级（20）放大，放大的第一输入信号耦合到输出放大器，零级自动归零到第二个电压电平，第二个输入信号被第三个自动归零状态放大并且放大的第二输入信号在第四阶段（D）期间耦合到输出放大器。

6. 发明申请

WO2007100406A2 REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION 审中-公开
标题翻译：减少PIN码扫描链实现
公开(公告)号：WO2007100406A2
公开(公告)日：2007-09-07
申请号：PCT/US2006/061857
申请日：2006-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED , DOORENBOS, Jerry, L. , TRIFONOV, Dimitar , GARDNER, Marco, A.
发明人： DOORENBOS, Jerry, L. , TRIFONOV, Dimitar , GARDNER, Marco, A.
CPC分类号： G01R31/318536 , G01R31/3172
摘要： The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops (SDC0, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataIn); a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut). In one embodiment, the scan data input signal and the scan data output signal share an input/output pin.
摘要翻译：具有减少引脚数扫描链的同步逻辑器件包括：多于两个触发器（SDC0，SDC1，SDC2）耦合以形成用于接收扫描数据输入信号（ScanDataIn）的移位寄存器; 用于接收设备输入的组合逻辑电路（20），为所述多于两个的触发器产生触发器/触发器输入，并产生输出信号; 用于在测试模式期间向多于两个触发器提供时钟信号的第一多路复用器（MUX10）第二多路复用器（MUX12），用于在从移位寄存器输出的测试模式与来自组合逻辑电路（20）的输出信号之间进行选择，以及用于提供扫描数据输出信号（ScanDataOut）。在一个实施例中，扫描数据输入信号和扫描数据输出信号共享输入/输出引脚。

7. 发明申请

WO2011133192A1 BANDGAP REFERENCE CIRCUIT AND METHOD 审中-公开
标题翻译：带宽参考电路和方法
公开(公告)号：WO2011133192A1
公开(公告)日：2011-10-27
申请号：PCT/US2010/061421
申请日：2010-12-21
申请人： TEXAS INSTRUMENTS INCORPORATED , TRIFONOV, Dimitar, T. , DOORENBOS, Jerry, L. , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： TRIFONOV, Dimitar, T. , DOORENBOS, Jerry, L.
IPC分类号： G05F3/02 , G05F3/20
CPC分类号： G05F3/30 , H03F1/303 , H03F2200/447
摘要： A circuit for generating a band gap reference voltage (VREF) includes circuitry (I 3 X7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0x 16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small V BE voltages on the second conductor. The relatively large and small V BE voltages provide differential band gap charges (Q CA -Q CB ) which are averaged to provide a stable band gap reference voltage (V REF ).
摘要翻译：用于产生带隙基准电压（VREF）的电路包括用于向第一导体（NODE1）提供第一电流的电路（I3X7）和向第二导体（NODE2）提供第二电流的电路。第一导体响应于数字信号（CTL-VBE）分别依次耦合到多个二极管（Q0x16），以使第一电流依次流入选定的二极管。第二导体耦合到当前不耦合到第一导体的二极管的集电极。二极管连续地耦合到第一导体，使得第一电流分别导致二极管在第一导体上产生相对较大的VBE电压，而第二电流使二极管组不耦合到第一导体以产生较小的VBE 第二导体上的电压。相对较大和较小的VBE电压提供差分带隙电荷（QCA-QCB），其平均以提供稳定的带隙参考电压（VREF）。

8. 发明申请

WO2008055139A2 DIGITAL-TO-ANALOG CONVERTER ARCHITECTURE AND METHOD HAVING LOW SWITCH COUNT AND SMALL OUTPUT IMPEDANCE 审中-公开
标题翻译：具有低开关量和小输出阻抗的数字到模拟转换器架构和方法
公开(公告)号：WO2008055139A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/082970
申请日：2007-10-30
申请人： TEXAS INSTRUMENTS INCORPORATED , TRIFONOV, Dimitar, T. , DOORENBOS, Jerry, L.
发明人： TRIFONOV, Dimitar, T. , DOORENBOS, Jerry, L.
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765 , H03M1/785
摘要： A digital-to-analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (VO) to produce coarse resolution node voltages (V0,...V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,l...) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Voutl), the second output voltage (Voutl) and the first output voltage (Vout2) providing a differential analog output signal (Voutl -Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R- 2R networks.
摘要翻译：数模转换器包括耦合在第一电压（Vin）和中间电压（VO）之间以产生粗分辨率节点电压（V0，... V240）的粗分辨率电阻器电路（11），并且还包括耦合在中间电压和第二电压（GND）之间的精细分辨率电阻电路（20）。响应于数字输入（D0,1 ...）的一组MSB位来选择粗分辨率节点电压之一以产生第一输出电压（Vout2），并且选择精细分辨率节点电压中的一个响应于数字输入的一组LSB位以产生第二输出电压（Vout1），第二输出电压（Vout1）和提供差分模拟输出信号（Vout1 -Vout2）的第一输出电压（Vout2）。在一个实施例中，粗分辨率和精细分辨率电阻器电路是串电阻电路，在另一实施例中，它们是修改的R 2R网络。

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