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1. 发明申请

WO2006018762A3 DUAL GATE CMOS FABRICATION 审中-公开
公开(公告)号：WO2006018762A3
公开(公告)日：2006-02-23
申请号：PCT/IB2005/052569
申请日：2005-08-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MULLER, Markus , STOLK, Peter
发明人： MULLER, Markus , STOLK, Peter
IPC分类号： H01L21/8238 , H01L29/49
摘要： The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

2. 发明申请

WO2006018762A2 DUAL GATE CMOS FABRICATION 审中-公开
标题翻译：双门CMOS制造
公开(公告)号：WO2006018762A2
公开(公告)日：2006-02-23
申请号：PCT/IB2005052569
申请日：2005-08-01
申请人： KONINKL PHILIPS ELECTRONICS NV , MULLER MARKUS , STOLK PETER
发明人： MULLER MARKUS , STOLK PETER
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975 , H01L29/66545
摘要： The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.
摘要翻译：本发明涉及一种制造CMOS器件的方法，包括提供其中具有绝缘材料层（102）的半导体衬底（101），该方法包括在绝缘层（102）上提供第一材料层（106）），第一材料的层（106）的厚度在用于支撑第一有源器件的第一区域（103）中比在用于支撑第二有源器件的第二区域（104）中更小。然后将第二材料的层（107）沉积在第一材料的层（106）上，然后对该结构进行热处理以使第一和第二材料合金化。第一区域上的层的部分完全合金化，而第二区域上的部分层不是，使得第一材料的层（106）的一部分（109）保留。

3. 发明申请

WO03046967A3 METHOD OF FORMING A DOPED REGION IN A SEMICONDUCTOR BODY COMPRISING A STEP OF AMORPHIZATION BY IRRADIATION 审中-公开
标题翻译：在包含通过辐照的扩增步骤的半导体体中形成掺杂区的方法
公开(公告)号：WO03046967A3
公开(公告)日：2003-10-16
申请号：PCT/IB0204881
申请日：2002-11-20
申请人： KONINKL PHILIPS ELECTRONICS NV , STOLK PETER A
发明人： STOLK PETER A
IPC分类号： H01L21/20 , H01L21/225 , H01L21/265 , H01L21/268 , H01L21/324 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L21/263
CPC分类号： H01L29/66575 , H01L21/26513 , H01L21/2652 , H01L21/268 , H01L21/324
摘要： In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.
摘要翻译：在制造具有半导体本体（2）的半导体器件（1）的方法中，在半导体本体（2）中形成掺杂区（3）。半导体本体（2）具有晶体表面区域（4），该晶体表面区域（4）至少部分非晶化，以形成非晶表面层（5）。非晶化是通过用由结晶表面区域（4）吸收的辐射脉冲（7）照射表面（6）来实现的。辐射脉冲（7）具有选择为使得辐射被结晶表面区域（4）吸收的波长，并且选择辐射脉冲（7）的能量通量使得晶体表面层（5）为融化了。该方法可用于制造超浅结。

4. 发明申请

WO2005076331A1 METHOD OF FABRICATING METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES. 审中-公开
标题翻译：制备金属氧化物半导体集成电路器件的方法。
公开(公告)号：WO2005076331A1
公开(公告)日：2005-08-18
申请号：PCT/IB2005/000248
申请日：2005-01-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , STOLK, Peter , PONOMAREV, Youri
发明人： STOLK, Peter , PONOMAREV, Youri
IPC分类号： H01L21/28
CPC分类号： H01L29/517 , H01L21/26506 , H01L21/28167 , H01L21/28176 , H01L21/28194 , H01L21/324 , H01L21/823807 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/518
摘要： The present invention relates to a method of fabricating metal-oxide semiconductor integrated circuit devices. Said fabrication method comprises the steps of: - forming a dielectric layer (111) on a substrate, - forming a gate electrode (112) on said dielectric layer, - implanting passivating impurities (121) in the substrate, and - performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment. The gate electrode is, for example, a metallic gate electrode. The step of implanting passivating impurities in the substrate is performed, for example, through the metallic gate electrode and the dielectric layer. The passivating impurities are chosen, for example, among hydrogen, deuterium, fluorine, nitrogen or chlorine.
摘要翻译：本发明涉及金属氧化物半导体集成电路器件的制造方法。所述制造方法包括以下步骤： - 在衬底上形成电介质层（111）， - 在所述电介质层上形成栅电极（112）， - 在所述衬底中注入钝化杂质（121），以及 - 执行热处理所述钝化杂质适于在所述热处理期间钝化介电层内的介电缺陷。栅电极例如是金属栅电极。在衬底中注入钝化杂质的步骤例如通过金属栅电极和电介质层进行。选择钝化杂质，例如氢，氘，氟，氮或氯。

5. 发明申请

WO2004086508A1 IMPROVED GATE ELECTRODE FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件的改进的栅极电极
公开(公告)号：WO2004086508A1
公开(公告)日：2004-10-07
申请号：PCT/IB2004/050321
申请日：2004-03-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu, C. , STOLK, Peter, A.
发明人： SURDEANU, Radu, C. , STOLK, Peter, A.
IPC分类号： H01L29/49
CPC分类号： H01L29/4925
摘要： The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a second side oriented away from the substrate, the first layer of activated crystalline gate material having a doping level of 10 19 ions/cm 3 or higher, and a second layer of gate material at the second side of the first layer of activated crystalline gate material. The present invention also provides a method for making such a device.
摘要翻译：本发明提供了一种MIS型半导体器件，包括半导体衬底和形成在栅极绝缘膜上并由栅极材料形成的栅电极。栅极电极包括：第一激活晶体栅极材料层，其具有朝向衬底取向的第一侧和远离衬底取向的第二侧，所述第一层激活的晶体栅极材料具有10 / cm 3以上，第二层栅极材料在第一层激活的结晶栅极材料的第二侧。本发明还提供了制造这种装置的方法。

6. 发明申请

WO2003046967A2 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2003046967A2
公开(公告)日：2003-06-05
申请号：PCT/IB2002/004881
申请日：2002-11-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , STOLK, Peter, A.
发明人： STOLK, Peter, A.
IPC分类号： H01L21/268
CPC分类号： H01L29/66575 , H01L21/26513 , H01L21/2652 , H01L21/268 , H01L21/324
摘要： In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.
摘要翻译：在制造具有半导体本体（2）的半导体器件（1）的方法中，在半导体本体（2）中形成掺杂区（3）。半导体本体（2）具有晶体表面区域（4），该晶体表面区域（4）至少部分非晶化，以形成非晶表面层（5）。非晶化是通过用由结晶表面区域（4）吸收的辐射脉冲（7）照射表面（6）来实现的。辐射脉冲（7）具有选择为使得辐射被结晶表面区域（4）吸收的波长，并且选择辐射脉冲（7）的能量通量使得晶体表面层（5）为融化了。该方法可用于制造超浅结。

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