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1. 发明申请

WO03046967A3 METHOD OF FORMING A DOPED REGION IN A SEMICONDUCTOR BODY COMPRISING A STEP OF AMORPHIZATION BY IRRADIATION 审中-公开
标题翻译：在包含通过辐照的扩增步骤的半导体体中形成掺杂区的方法
公开(公告)号：WO03046967A3
公开(公告)日：2003-10-16
申请号：PCT/IB0204881
申请日：2002-11-20
申请人： KONINKL PHILIPS ELECTRONICS NV , STOLK PETER A
发明人： STOLK PETER A
IPC分类号： H01L21/20 , H01L21/225 , H01L21/265 , H01L21/268 , H01L21/324 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L21/263
CPC分类号： H01L29/66575 , H01L21/26513 , H01L21/2652 , H01L21/268 , H01L21/324
摘要： In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.
摘要翻译：在制造具有半导体本体（2）的半导体器件（1）的方法中，在半导体本体（2）中形成掺杂区（3）。半导体本体（2）具有晶体表面区域（4），该晶体表面区域（4）至少部分非晶化，以形成非晶表面层（5）。非晶化是通过用由结晶表面区域（4）吸收的辐射脉冲（7）照射表面（6）来实现的。辐射脉冲（7）具有选择为使得辐射被结晶表面区域（4）吸收的波长，并且选择辐射脉冲（7）的能量通量使得晶体表面层（5）为融化了。该方法可用于制造超浅结。

2. 发明申请

WO0077828A2 A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO0077828A2
公开(公告)日：2000-12-21
申请号：PCT/EP0005012
申请日：2000-05-31
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： STOLK PETER A , PONOMAREV YOURI
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/51 , H01L29/78 , H01L
CPC分类号： H01L29/4983 , H01L21/2807 , H01L21/28105 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583 , H01L29/6659
摘要： In a method of manufacturing a semiconductor device comprising a transistor having a gate (22) insulated from a channel (13) by a gate dielectric (17), which channel (13) is provided in an active region (4) of a first conductivity type provided at a surface (2) of a semiconductor body (1) and has a length L over which it extends between a source zone (11,9) and a drain zone (12,9) of a second conductivity type, the active region (4) of the first conductivity type is defined in the semiconductor body (1), and a dielectric layer (14) is applied which is provided with a recess at the area of the gate (22) planned to be provided at a later stage, in which recess an insulating layer is applied, forming the gate dielectric (17) of the transistor. Then, a first conductive layer and a second conductive layer are applied, the first conductive layer being relatively thin compared to the width of the recess, which first conductive layer and second conductive layer jointly form the gate (22) of the transistor and fill the recess in the dielectric layer (14). The gate comprises a central portion (21) and side end portions (19) positioned along either side of the central portion (21), which central portion (21) and side end portions (19) are in contact with the gate dielectric (17) and jointly establish a work function of the gate (22) varying across the length L of the channel (13).
摘要翻译：在制造半导体器件的方法中，该半导体器件包括具有通过栅极电介质（17）与沟道（13）绝缘的栅极（22）的晶体管，该沟道（13）设置在第一导电性的有源区（4）中类型设置在半导体本体（1）的表面（2）处，并且具有在第二导电类型的源极区（11,9）和漏极区（12,9）之间延伸的长度L，活性第一导电类型的区域（4）被限定在半导体本体（1）中，并且施加介电层（14），其在门（22）的区域处设置有凹口，该区域被设计成稍后在其中施加绝缘层的凹部中，形成晶体管的栅极电介质（17）。然后，施加第一导电层和第二导电层，第一导电层与凹槽的宽度相比较薄，第一导电层和第二导电层共同形成晶体管的栅极（22），并填充凹陷在介电层（14）中。门包括中心部分（21）和沿中心部分（21）的任一侧定位的侧端部分（19），该中心部分（21）和侧端部分（19）与栅极电介质（17）接触）并且共同建立在通道（13）的长度L上变化的门（22）的功能。

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