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1. 发明申请

WO2004112126A1 A METHOD OF PREPARATION OF AN EPITAXIAL SUBSTRATE 审中-公开
标题翻译：一种外源基质的制备方法
公开(公告)号：WO2004112126A1
公开(公告)日：2004-12-23
申请号：PCT/EP2004/005439
申请日：2004-05-19
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A. , FAURE, Bruce
发明人： FAURE, Bruce
IPC分类号： H01L21/78
CPC分类号： C30B25/183 , H01L21/76254 , Y10S117/915
摘要： The invention relates to a method of preparation of an epitaxial substrate, in particular a GaN, a SiGe, AIN or InN epitaxial substrate. It is the object of the present invention to provide a process of preparation of an epitaxial substrate which further reduces the influence of the substrate while being at the same time economically viable. The object is solved by providing a base substrate, implanting atomic species in the base substrate to create a weak layer like zone, providing an epitaxial stiffening layer on a surface of a base substrate at a first temperature and isolating the stiffening layer at a second higher temperature, in particular together with a sub-layer of the base substrate, from the remainder of the base substrate, whereby the isolated material creates a pseudo substrate on which a homo- or heteroepitaxial layer is provided.
摘要翻译：本发明涉及外延衬底，特别是GaN，SiGe，AlN或InN外延衬底的制备方法。本发明的目的是提供一种外延衬底的制备方法，其进一步降低了衬底的影响，同时在经济上是可行的。该目的通过提供一种基底衬底来解决，在基底衬底中注入原子物质以产生类似薄层的区域，在第一温度下在基底衬底的表面上提供外延加强层，并在第二高度隔离加强层温度，特别是与基底衬底的子层一起，与基底衬底的其余部分相结合，从而隔离材料产生伪衬底，在其上提供均一或异质外延层。

2. 发明申请

WO2012003157A1 SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME 审中-公开
标题翻译：具有强化层的玻璃基板上的半导体及其制造方法
公开(公告)号：WO2012003157A1
公开(公告)日：2012-01-05
申请号：PCT/US2011/042068
申请日：2011-06-28
申请人： CORNING INCORPORATED , SILICON ON INSULATOR TECHNOLOGIES S.A. , CHUANG, Ta Ko , CITES, Jeffrey S. , DELPRAT, Daniel , MOHAMED, Nadia B. , USENKO, Alex
发明人： CHUANG, Ta Ko , CITES, Jeffrey S. , DELPRAT, Daniel , MOHAMED, Nadia B. , USENKO, Alex
IPC分类号： H01L21/762
CPC分类号： H01L29/02 , H01L21/185 , H01L21/762 , H01L21/76254
摘要： A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.
摘要翻译：一种半导体玻璃衬底，其具有相对较硬（例如相对较高的杨氏模量为125或更高）的加强层或者放置在硅膜和玻璃之间的层，以消除否则在表面上形成的峡谷和针孔在离子注入薄膜转移过程中转移的硅膜。新的加强层可以由诸如氮化硅的材料形成，其也用作有效阻挡钠和其它有害杂质从玻璃基板渗透到硅膜中的有效屏障。

3. 发明申请

WO2008014079A1 STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
标题翻译：半导体缓冲器结构中的应变层
公开(公告)号：WO2008014079A1
公开(公告)日：2008-01-31
申请号：PCT/US2007/072252
申请日：2007-06-27
申请人： ASM AMERICA, INC. , S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
发明人： CODY, Nyles, W. , FIGUET, Christophe , KENNARD, Mark
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532
摘要： A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
摘要翻译：包括衬底10的半导体工件，包括形成在衬底上的渐变部分的松弛缓冲层14,18以及松弛缓冲层14,18的渐变部分内的至少一个应变过渡层16及其制造方法。至少一个应变过渡层16由于缓冲缓冲层14,18相对于衬底10的CTE收缩的差异热膨胀系数（CTE）收缩而减少了工件弓形的数量。

4. 发明申请

WO2006074933A1 METHOD OF PRODUCING A SUBSTRATE FOR AN OPTOELECTRONIC APPLICATION 审中-公开
标题翻译：生产用于光电子应用的基板的方法
公开(公告)号：WO2006074933A1
公开(公告)日：2006-07-20
申请号：PCT/EP2006/000230
申请日：2006-01-12
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. , LETERTRE, Fabrice , FAURE, Bruce
发明人： LETERTRE, Fabrice , FAURE, Bruce
IPC分类号： H01L21/20 , H01L33/00
CPC分类号： H01L31/1892 , H01L21/2007 , H01L21/76254 , H01L33/0079 , Y02E10/50
摘要： The present invention relates to a method of producing a substrate for an optoelectronic application, the substrate having at least one active nitride layer on a final carrier and a metallic intermediate layer therebetween, wherein the method comprises: preparation of an auxiliary substrate wherein one semi-conducting nitride layer is placed on an auxiliary carrier; metallising the auxiliary substrate on the side of the nitride layer; bonding of the metallised carrier substrate with the final carrier; and removing of the auxiliary carrier after the bonding step. It is the object of the present invention to provide a method of this type in which the crystalline quality of the active nitride layer(s) can be improved. The object is solved by a method of the above mentioned type wherein the step of preparing the auxiliary substrate comprises: detaching a part from a massive semi-conducting nitride substrate; and transferring said part onto the auxiliary carrier to form the semi-conducting nitride layer thereon.
摘要翻译：本发明涉及一种制备光电子应用基片的方法，该基底在最终载体上具有至少一个活性氮化物层和其间的金属中间层，其中所述方法包括：制备辅助基底，其中，导电氮化物层放置在辅助载体上; 在氮化物层的侧面对辅助衬底进行金属化; 金属化载体基板与最终载体的接合; 以及在接合步骤之后去除辅助载体。本发明的目的是提供一种可以提高活性氮化物层的结晶质量的方法。该目的通过上述类型的方法来解决，其中准备辅助衬底的步骤包括：从块状半导体氮化物衬底分离一部分; 并将所述部分转移到辅助载体上以在其上形成半导电氮化物层。

5. 发明申请

WO2007133358A2 SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
公开(公告)号：WO2007133358A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/008879
申请日：2007-04-09
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A. , CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
发明人： CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
IPC分类号： C23C16/22 , C23C16/455 , C30B29/02 , C30B25/14
CPC分类号： C23C16/22 , C23C16/24 , C23C16/45523 , C30B25/165 , C30B29/52
摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
摘要翻译：通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。在形成渐变的SiGe缓冲层期间，从硅前体和锗前体的SiGe的沉积被中断一次或多次，其中停止向硅衬底的硅前驱体的流动，同时锗前体流向保持底物。

6. 发明申请

WO2006086024A1 RELAXATION OF A STRAINED LAYER USING A MOLTEN LAYER 审中-公开
标题翻译：使用薄层的应变层的放松
公开(公告)号：WO2006086024A1
公开(公告)日：2006-08-17
申请号：PCT/US2005/039174
申请日：2005-10-31
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. , CELLER, George, K.
发明人： CELLER, George, K.
IPC分类号： H01L21/20
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/2026 , Y10S438/938
摘要： A method for making a crystalline wafer, in which an interface layer is associated with a support substrate. A first layer is associated with the interface layer in a strained state. The interface layer is melted sufficiently to substantially uncouple the first layer from the support substrate to relax the first layer from the strained state to a relaxed state. The interface material is solidified with the first layer in the relaxed state to obtain a first wafer.
摘要翻译：一种用于制造晶体晶片的方法，其中界面层与支撑衬底相关联。第一层与处于紧张状态的界面层相关联。界面层被充分熔化以使第一层基本上与支撑衬底分离，以将第一层从应变状态松弛至松弛状态。界面材料在松弛状态下与第一层固化以获得第一晶片。

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