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1. 发明申请

WO2007140288A2 FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 审中-公开
标题翻译：使用块状半导体波形形成改进的SOI衬底
公开(公告)号：WO2007140288A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069720
申请日：2007-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , HENSON, William, K. , NG, Hung, Y. , RIM, Kern , WANN, Clement, H.
发明人： CHIDAMBARRAO, Dureseti , HENSON, William, K. , NG, Hung, Y. , RIM, Kern , WANN, Clement, H.
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions (2, 4, 6). Each device region comprises at least a base semiconductor substrate layer (12) and a semiconductor device layer (16) with a buried insulator layer (14) located therebetween, while the semiconductor device layer (16) is supported by one or more vertical insulating pillars (22). The vertical insulating pillars (22) each preferably has a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by one or more vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).
摘要翻译：本发明涉及具有一个或多个器件区域（2,4,6）的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层（12）和半导体器件层（16），其中位于其间的掩埋绝缘体层（14），而半导体器件层（16）由一个或多个垂直绝缘柱（22）。垂直绝缘柱（22）各自优选地具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由一个或多个垂直绝缘体柱（22）。气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

2. 发明申请

WO2004114400A1 HIGH-PERFORMANCE CMOS SOI DEVICE ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 审中-公开
标题翻译：高性能CMOS SOI器件在混合晶体导向衬底上的应用
公开(公告)号：WO2004114400A1
公开(公告)日：2004-12-29
申请号：PCT/EP2004/050946
申请日：2004-05-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , Compagnie IBM FRANCE , DORIS, Bruce , GUARINI, Kathryn , LEONG, MeiKei , NARASIMHA, Shreesh , RIM, Kern , SLEIGHT, Jeffrey, W. , YANG, Min
发明人： DORIS, Bruce , GUARINI, Kathryn , LEONG, MeiKei , NARASIMHA, Shreesh , RIM, Kern , SLEIGHT, Jeffrey, W. , YANG, Min
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material isregrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on theregrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并且半导体材料被暴露在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，在其上形成第二半导体器件。

3. 发明申请

WO2007112432A3 EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
标题翻译：通过超弹性非晶态材料退火的硅碳取代固体溶液外延
公开(公告)号：WO2007112432A3
公开(公告)日：2009-03-26
申请号：PCT/US2007065324
申请日：2007-03-28
申请人： IBM , LIU YAOCHENG , GLUSCHENKOV OLEG , RIM KERN , MADAN ANITA , HOLT JUDSON
发明人： LIU YAOCHENG , GLUSCHENKOV OLEG , RIM KERN , MADAN ANITA , HOLT JUDSON
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/2022 , H01L21/2026 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y
摘要翻译：可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。退火优选是闪光退火或激光退火。该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

4. 发明申请

WO2008014038A1 FULLY SILICIDED GATE ELECTRODES AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：全硅酸盐电极及其制造方法
公开(公告)号：WO2008014038A1
公开(公告)日：2008-01-31
申请号：PCT/US2007/068652
申请日：2007-05-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HENSON, William, K. , RIM, Kern
发明人： HENSON, William, K. , RIM, Kern
IPC分类号： H01L21/4763
CPC分类号： H01L21/28097 , H01L21/28052 , H01L21/324 , H01L21/823835 , H01L21/823842 , H01L29/4941 , H01L29/4975 , H01L29/517 , H01L29/665
摘要： The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully suiciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are compatible with workfunctions that are different from conventional n+ and p+ doped poly silicon electrodes. Each device region consists of at least one Field Effect Transistor (FET) device which consists of either a polysilicon gate electrode or a fully suicided (FUSI) gate electrode. A gate electrode comprised of silicon and a Ge containing layer is used in combination with a selective removal process of the Ge containing layer. The Ge containing layer is not removed on devices with threshold voltages that are not compatible with the FUSI workfunction. Devices that are compatible with the FUSI workfunction have the Ge containing layer removed prior to the junction silicidation step. The remaining thin silicon layer of the gate electrode becomes fully suicided during the same step as the junction silicidation step.
摘要翻译：本发明涉及一种通过完全自动（FUSI）栅极选择性地在一个或多个器件区域中制造金属栅电极的方法。 FUSI的选择性形成使得能够在与常规n +和p +掺杂多晶硅电极不同的工作功能兼容的器件上制造金属栅电极。每个器件区域由至少一个场效应晶体管（FET）器件组成，该器件由多晶硅栅极电极或全自动（FUSI）栅电极组成。与含锗层的选择性去除方法结合使用由硅和含Ge层组成的栅电极。在与FUSI功能不兼容的阈值电压的器件上，Ge含量层不被去除。与FUSI功能功能兼容的器件在接合硅化步骤之前已除去Ge含量层。在与连接硅化步骤相同的步骤中，栅电极的剩余薄硅层变得完全自发。

5. 发明申请

WO2006006972A1 IMPROVED STRAINED-SILICON CMOS DEVICE AND METHOD 审中-公开
标题翻译：改进的应变硅CMOS器件和方法
公开(公告)号：WO2006006972A1
公开(公告)日：2006-01-19
申请号：PCT/US2005/011661
申请日：2005-04-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BRYANT, Andres , OUYANG, Qiqing , RIM, Kern
发明人： BRYANT, Andres , OUYANG, Qiqing , RIM, Kern
IPC分类号： H01L29/10
CPC分类号： H01L29/165 , H01L29/1054 , H01L29/24 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a reduced substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在还原的底物中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

6. 发明申请

WO2012050653A1 METHOD AND STRUCTURE FOR pFET JUNCTION PROFILE WITH SiGe CHANNEL 审中-公开
标题翻译：用于SiGe通道的pFET结构剖面的方法和结构
公开(公告)号：WO2012050653A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/045446
申请日：2011-07-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , RIM, Kern , HENSON, William, K. , LIANG, Yue , WANG, Xinlin
发明人： RIM, Kern , HENSON, William, K. , LIANG, Yue , WANG, Xinlin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/6659
摘要： A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel 14 is provided in which the junction profile of the source region and the drain region 26 is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer 16 directly beneath a SiGe channel layer 14 which is located above a Si substrate 12. A structure is thus provided in which the N- or C-doped Si layer 16 (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer 14 have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer 16 retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
摘要翻译：提供了包括位于硅锗（SiGe）沟道14的表面上的p沟道场效应晶体管（pFET）器件的半导体结构，其中源极区域和漏极区域26的接合轮廓突然。在本公开内容中，通过在位于Si衬底12上方的SiGe沟道层14的正下方形成N或C掺杂的Si层16来提供用于pFET器件的突发源极/漏极结。因此，提供了一种结构，其中 N-或C掺杂的Si层16（夹在SiGe沟道层和Si衬底之间）对于p型掺杂剂具有与覆盖的SiGe沟道层大致相同的扩散速率。由于N或C掺杂的Si层和上覆的SiGe沟道层14对于p型掺杂物具有基本相同的扩散率，并且由于N或C掺杂的Si层16阻止p型掺杂剂的扩散进入下面的Si衬底，可以形成突然的源极/漏极结。

7. 发明申请

WO2008014228A2 RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 审中-公开
标题翻译：用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术
公开(公告)号：WO2008014228A2
公开(公告)日：2008-01-31
申请号：PCT/US2007/074169
申请日：2007-07-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAKRAVARTI, Ashima, B. , CHIDAMBARRAO, Dureseti , HOLT, Judson, R. , LIU, Yaocheng , RIM, Kern
发明人： CHAKRAVARTI, Ashima, B. , CHIDAMBARRAO, Dureseti , HOLT, Judson, R. , LIU, Yaocheng , RIM, Kern
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

8. 发明申请

WO2007112432A2 EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
标题翻译：通过超弹性非晶态材料退火的硅碳取代固体溶液外延
公开(公告)号：WO2007112432A2
公开(公告)日：2007-10-04
申请号：PCT/US2007/065324
申请日：2007-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LIU, Yaocheng , GLUSCHENKOV, Oleg , RIM, Kern , MADAN, Anita , HOLT, Judson
发明人： LIU, Yaocheng , GLUSCHENKOV, Oleg , RIM, Kern , MADAN, Anita , HOLT, Judson
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02667 , H01L21/02524 , H01L21/2022 , H01L21/2026 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si 1-y C y , y
摘要翻译：可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。退火优选是闪光退火或激光退火。该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。该方法在CMOS工艺和其它电子器件制造中特别有用，其中外延Si 1-y C y y y的存在y <0.1是应变工程或带隙工程所需的。

9. 发明申请

WO2004077509A3 SHALLOW TRENCH ISOLATION STRUCTURE FOR STRAINED Si ON SiGe 审中-公开
标题翻译：应变硅SiGe上的浅沟槽隔离结构
公开(公告)号：WO2004077509A3
公开(公告)日：2004-10-21
申请号：PCT/US2004005020
申请日：2004-02-20
申请人： IBM , KOESTER STEVEN , BEYER KLAUS , HARGROVE MICHAEL , RIM KERN , CHAN KEVIN
发明人： KOESTER STEVEN , BEYER KLAUS , HARGROVE MICHAEL , RIM KERN , CHAN KEVIN
IPC分类号： H01L21/762 , H01L29/786
CPC分类号： H01L29/7842 , H01L21/76224 , H01L29/78687
摘要： A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.
摘要翻译：公开了用于隔离电子设备的结构和用于制造该结构的方法。电子器件在包括应变Si层下方的SiGe基础层的衬底中进行处理。隔离结构包括从衬底顶表面向下延伸并穿透SiGe基层的沟槽，在衬底中形成侧壁。外延Si衬垫被选择性地沉积到沟槽侧壁上，并且随后被热氧化。沟槽填充有沟槽电介质，其突出于衬底顶表面之上。

10. 发明申请

WO2008085686A2 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE 审中-公开
标题翻译：具有硅酸盐的移动增强MOSFET的结构和方法
公开(公告)号：WO2008085686A2
公开(公告)日：2008-07-17
申请号：PCT/US2007088266
申请日：2007-12-20
申请人： IBM , LIU YAOCHANG , CHIDAMBARRAO DURESETI , RIM KERN , GLUSCHENKOV OLEG , MO RENEE T , HOLT JUDSON R
发明人： LIU YAOCHANG , CHIDAMBARRAO DURESETI , RIM KERN , GLUSCHENKOV OLEG , MO RENEE T , HOLT JUDSON R
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

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