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1. 发明申请

WO1981003573A1 DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器的解码器电路
公开(公告)号：WO1981003573A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000670
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C11/40
CPC分类号： G11C8/10 , G11C11/418
摘要： A decoder circuit (66) includes a plurality of input transistors (78-86) connected to address lines (68-76). The drain terminals of the input transistors (78-86) are connected to a first power terminal and the source terminals thereof are connected to a first node (92) which is charged to low voltage state upon receipt of a precharge signal at a transistor (94). An address enable signal (58) operates a transistor (96) to connect node (92) to node (98) during receipt of the address. A node (102) is charged to a high state by operation of a transistor (100) in response to a precharge signal (56). Node (102) is discharged through a transistor (104) when a high voltage state is present at the node (98). An enable clock signal (52) is transmitted through a transistor (106) to a row line (108) when a high voltage state is present on node (102).
摘要翻译：解码器电路（66）包括连接到地址线（68-76）的多个输入晶体管（78-86）。输入晶体管（78-86）的漏极端子连接到第一电源端子，并且其源极端子连接到第一节点（92），该第一节点在晶体管上接收到预充电信号时被充电到低电压状态 94）。地址使能信号（58）在接收地址期间操作晶体管（96）以将节点（92）连接到节点（98）。响应于预充电信号（56），通过晶体管（100）的操作将节点（102）充电到高电平。当节点（98）存在高电压状态时，节点（102）通过晶体管（104）放电。当节点（102）上存在高电压状态时，使能时钟信号（52）通过晶体管（106）传输到行线（108）。

2. 发明申请

WO1981003572A1 SEMICONDUCTOR MEMORY PRECHARGE CIRCUIT 审中-公开
标题翻译：半导体存储器预置电路
公开(公告)号：WO1981003572A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000671
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C07/06
CPC分类号： G11C11/419 , G11C11/4094
摘要： A semiconductor memory circuit has half digit lines (116, 118) which are connected to a sense amplifier (120). A memory cell (122) produces a voltage offset on a half digit line (116). The sense amplifier (120) pulls the half digit line (116, 118) with the lower voltage to ground. Pull up circuits (126, 128) act to pull the half digit line (116, 118) with the higher voltage up to the supply voltage. After the pull up operation a precharge signal (84) activates a pair of precharge transistors (132, 134) which couple the half digit lines (116, 118) to a common latch node (110). The voltages on the half digit lines (116, 118) equilibrate by current flow through the latch node (110).
摘要翻译：半导体存储器电路具有连接到读出放大器（120）的半数位线（116,118）。存储单元（122）在半数位线（116）上产生电压偏移。读出放大器（120）将较低电压的半数位线（116,118）拉到地。上拉电路（126,128）用于以更高的电压拉到半数字线（116,118）直到电源电压。在上拉操作之后，预充电信号（84）激活将半数位线（116,118）耦合到公共锁存节点（110）的一对预充电晶体管（132,134）。半数位线（116,118）上的电压通过通过锁存节点（110）的电流平衡。

3. 发明申请

WO1982000896A1 GO/NO GO MARGIN TEST CIRCUIT FOR SEMICONDUCTOR MEMORY 审中-公开
标题翻译：进入/停止半导体存储器的测试电路
公开(公告)号：WO1982000896A1
公开(公告)日：1982-03-18
申请号：PCT/US1980001150
申请日：1980-09-08
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G01R31/28
CPC分类号： G11C29/50 , G01R31/3161 , G06F2201/81 , G11C2029/5004
摘要： A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each connected to one input of a sense amplifier (146, 148). The sense amplifiers (146, 148) operate to pull one of the half digit lines connected thereto to ground while a pull up circuit (220) operates to elevate the other half digit line to the supply voltage. A margin test circuit receives through a control pin (236) an externally supplied test command which generates a test signal (318) to generate marginal low and marginal high voltage states to be written into the memory cells. The marginal low voltage state is generated by a voltage divider (288). The marginal high voltage state is generated by disabling the pull up circuit (220). To prevent loss of the marginal low state the sense amplifiers (146, 148 and 248) are disabled by the internally generated test signal. While the externally supplied test command is applied to the semiconductor memory circuit (140) marginal voltage states are applied to memory cells in accordance with externally supplied address and operational commands. The marginal voltage states are utilized to simplify testing of the circuit.
摘要翻译：半导体存储器电路（140）包括多个具有存取晶体管（154,158）和存储电容（162,166）的存储单元。存储单元连接到数字线（142,144），每个数字线被分成两半，每个连接到读出放大器（146,148）的一个输入。读出放大器（146,148）操作以在上拉电路（220）操作以将另一半数字线提升到电源电压的同时将连接到其的半数位线之一拉到地。裕度测试电路通过控制引脚（236）接收外部提供的测试命令，该测试命令产生测试信号（318）以产生要写入存储器单元的边际低电压和边缘高电压状态。边缘低电压状态由分压器（288）产生。通过禁止上拉电路（220）产生边际高电压状态。为了防止边缘低状态的损失，读出放大器（146,148和248）被内部产生的测试信号禁用。当向半导体存储器电路（140）施加外部提供的测试命令时，根据外部提供的地址和操作命令将边缘电压状态施加到存储器单元。边缘电压状态用于简化电路测试。

4. 发明申请

WO1981003570A1 SHARED QUIET LINE FLIP-FLOP 审中-公开
标题翻译：共享垂直线FLIP-FLOP
公开(公告)号：WO1981003570A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000675
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C07/02
CPC分类号： G11C11/419 , G11C8/08 , G11C11/4085
摘要： A quiet line flip-flop is connected to a plurality of lines (12, 14) for reducing the effect of capacitive coupling between the lines (12, 14) and a line (18). A node (26) is precharged by a transistor (34) to render conductive transistors (30, 32) which connect the respective lines (12, 14) to a ground node (24). When either of the lines (12, 14) is forced to a voltage above a preset voltage the corresponding transistors (22, 28) are respectively rendered conductive to discharge the node (26) which causes the transistors (30, 32) to be rendered nonconductive thereby disconnecting the lines (12, 14) from the ground node (24).
摘要翻译：一个静音触发器连接到多个线路（12,14），用于减少线路（12,14）和线路（18）之间的电容耦合的影响。节点（26）由晶体管（34）预充电以使导通晶体管（30,32）将各个线路（12,14）连接到接地节点（24）。当线路（12,14）中的任一个被强制到高于预设电压的电压时，相应的晶体管（22,28）分别导通以对节点（26）放电，从而使得晶体管（30,32）被渲染不导通，从而将线路（12,14）从接地节点（24）断开。

5. 发明申请

WO1982000937A1 SINGLE LAYER BURN-IN TAPE FOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路的单层烧录带
公开(公告)号：WO1982000937A1
公开(公告)日：1982-03-18
申请号：PCT/US1980001148
申请日：1980-09-08
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： H05K01/14
CPC分类号： G01R31/2863 , H01L23/4985 , H01L2924/0002 , H05K1/0266 , H05K1/11 , H05K3/0097 , H01L2924/00
摘要： A burn-in tape (48) includes a backing (50) and a pair of rectangular openings (56, 58) positioned transversely on the backing (50). Power conductors (52, 54) extend longitudinally on backing (50) outboard of the openings (56, 58). Additional conductor lines (104, 106) extend longitudinally along backing (50) between the openings (56, 58). Conductor strips (62, 70, 80, 88) connect the conductors (104, 52, 106, 54) to bonding pads (12, 20, 30, 38) on an integrated circuit (10). Signal conducting strips (64, 66, 68, 72, 74, 76, 78, 82, 84, 86, 90, 92, 94, 96) extend from corresponding test pads on backing (50) to bonding pads on the integrated circuit (10). The backing (50) is provided with sprocket holes (98) for precisely aligning the burn-in tape (48) with the integrated circuit (10). The conductors on the tape (48) provide a means for operating and thereby burning-in the components of the integrated circuit (10).
摘要翻译：老化胶带（48）包括背衬（50）和横向位于背衬（50）上的一对矩形开口（56,58）。电源导体（52,54）在开口（56,58）外侧的背衬（50）上纵向延伸。另外的导线（104,106）沿开口（56,58）之间的背衬（50）纵向延伸。导体条（62,70,80,88）将导体（104,52,106,54）连接到集成电路（10）上的接合焊盘（12,20,30,38）。信号导电条（64,66,68,72,74,76,78,82,84,86,90,92,94,96）从背衬（50）上的相应测试垫延伸到集成电路上的接合焊盘 10）。背衬（50）设置有用于将老化带（48）与集成电路（10）精确对准的链轮孔（98）。带（48）上的导体提供了一种用于操作并因此燃烧集成电路（10）的组件的装置。

6. 发明申请

WO1982000917A1 TAPE BURN-IN CIRCUIT 审中-公开
标题翻译：磁带刻录电路
公开(公告)号：WO1982000917A1
公开(公告)日：1982-03-18
申请号：PCT/US1980001149
申请日：1980-09-08
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C29/00
CPC分类号： G11C29/50
摘要： A circuit for burning-in an integrated circuit memory receives a two state signal at a burn-in terminal (168). A clock refresh signal is provided to a refresh terminal (170) which drives a refresh counter (192). A sequence of addresses are generated by the refresh counter (192) and provided to row decoders (194) and column decoders (196). When the burn-in command provided to the burn-in terminal (168) is at a first state, sense amplifiers (132) within a memory array (107) are disabled so that pullup circuits (148) elevate digit lines (116, 118) to a high voltage level. The high voltage level is transferred into memory cell storage capacitors (120, 122). When the burn-in command is in either the first or the second state, the refresh signal causes a row clock chain generator (176) to generate row clock signals and a column clock chain generator (178) to generate column clock signals. The addresses generated by the refresh counter together with the signals produced by the row and column clock generators cause the memory cells (120), sense amplifier (132) and associated circuitry within the memory array (107) to be burned-in. The memory array (107) can be exercised with signals received through only 4 terminals to make possible concurrent exercising of a plurality of integrated circuits on a tape having no crossovers of conductor lines.
摘要翻译：用于燃烧集成电路存储器的电路在老化端子（168）处接收两状态信号。时钟刷新信号被提供给驱动刷新计数器（192）的刷新终端（170）。地址序列由刷新计数器（192）产生并提供给行解码器（194）和列解码器（196）。当提供给老化终端（168）的老化指令处于第一状态时，存储器阵列（107）内的读出放大器（132）被禁用，使得上拉电路（148）提升数字线（116,118 ）达到高电平。高电压电平被传送到存储单元存储电容器（120,122）中。当老化命令处于第一或第二状态时，刷新信号使得行时钟链发生器（176）产生行时钟信号和列时钟链发生器（178）以产生列时钟信号。由刷新计数器产生的地址与行和列时钟发生器产生的信号一起导致存储器单元（120），读出放大器（132）和存储器阵列（107）内的相关电路被烧录。存储器阵列（107）可以通过仅通过4个端子接收的信号进行运行，以使得可以在不具有导线交叉的磁带上同时运行多个集成电路。

7. 发明申请

WO1981003569A1 SEMICONDUCTOR MEMORY DECODER WITH NONSELECTED ROW LINE HOLD DOWN 审中-公开
标题翻译：具有非选择线路的半导体存储器解码器保持下来
公开(公告)号：WO1981003569A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000674
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C07/02
CPC分类号： G11C8/08 , G11C11/418
摘要： A semiconductor memory decoder (10) includes an OR gate (12) which receives a multi-bit memory address. A node (26) is precharged to a low state and driven to a high state when the OR gate (12) is not selected by the address. A node (34) is precharged to a high state and pulled to ground when the node (26) is driven to a high state. The high state precharged on the node (34) is conveyed to anode (40) which is connected to the gate terminal of a row driver transistor (54) and to a node (46) which is connected to the gate terminal of a row driver transistor (64). The one of the nodes (40, 46) not connected to a selected row line is isolated from the node (34) to render conductive the corresponding nonselected row driver transistor (54, 64). A high voltage state row driver signal (RD0, RD1) is transmitted through the selected row driver transistor (54, 64) to charge the selected row line (56, 66). A low voltage state row driver signal is transmitted through the nonselected row driver transistor (54, 64) to hold the nonselected row line at ground.
摘要翻译：半导体存储器解码器（10）包括接收多位存储器地址的或门（12）。当没有由地址选择或门（12）时，节点（26）被预充电到低状态并被驱动到高电平状态。当节点（26）被驱动到高状态时，节点（34）被预充电到高状态并被拉到地。在节点（34）上预充电的高状态被传送到连接到行驱动晶体管（54）的栅极端子的阳极（40）和连接到行驱动器的栅极端子的节点（46）晶体管（64）。未连接到所选择的行线的节点（40,46）中的一个与节点（34）隔离，以使相应的非选择行驱动晶体管（54,64）导通。高电压状态行驱动器信号（RD0，RD1）通过选择的行驱动晶体管（54,64）传输，以对所选择的行线（56,66）充电。低电压状态行驱动器信号通过非选择行驱动晶体管（54,64）传输，以将未选择的行线保持在地。

8. 发明申请

WO1981003568A1 DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：动态随机存取存储器
公开(公告)号：WO1981003568A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000673
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R , WILSON D
发明人： MOSTEK CORP
IPC分类号： G11C07/00
CPC分类号： G11C11/4094
摘要： A dynamic random access memory (10) receives a memory address of a row decoder (14) which charges a selected row line (18). When the row line (18) is charged an access transistor (24) in a memory cell (22) is rendered conductive to connect a storage capacitor (26) to a bit line (30). The bit lines (30, 38) are previously set at an equilibration voltage. The voltage on the bit line (30) is driven slightly above the equilibration voltage if a high voltage state had been stored in the capacitor (26) or the voltage on the bit line is driven slightly below the equilibration voltage if a low voltage state had been stored on the capacitor (26). A sense amplifier (44) is connected to the bit lines (30, 38) and upon receipt of a latch signal (L) drives the one of the bit lines (30, 38) having the lower voltage to a low voltage state. A pullup circuit (60) drives the voltage on the remaining bit line of the pair to a high voltage state, restoring the memory storage capacitor (26) to its initial state. After the row line (18) is now discharged trapping the original data state in the storage capacitor (26), precharge transistors (50, 52) then connect together the bit lines (30, 38) through a latch node (46) to share charge between the bit lines (30, 38) and drive the bit lines (30, 38) to the equilibration voltage.
摘要翻译：动态随机存取存储器（10）接收对选定的行线（18）充电的行解码器（14）的存储器地址。当行线（18）被充电时，将存储单元（22）中的存取晶体管（24）导通以将存储电容器（26）连接到位线（30）。位线（30,38）预先设定为平衡电压。如果电容器（26）中存储高电压状态或位线上的电压略低于平衡电压，则位线（30）上的电压略高于平衡电压，如果低电压状态有被存储在电容器26上。读出放大器（44）连接到位线（30,38），并且在接收到具有较低电压的位线（30,38）之一的锁存信号（L）被驱动到低电压状态时。上拉电路（60）将该对的剩余位线上的电压驱动到高电压状态，将存储器存储电容器（26）恢复到初始状态。在行线（18）现在放电后，将原始数据状态捕获到存储电容器（26）中之后，预充电晶体管（50,52）然后通过锁存节点（46）将位线（30,38）连接在一起，以共享位线（30,38）之间的电荷并将位线（30,38）驱动到平衡电压。

9. 发明申请

WO1981003567A1 SEMICONDUCTOR MEMORY FOR USE IN CONJUNCTION WITH ERROR DETECTION AND CORRECTION CIRCUIT 审中-公开
标题翻译：用于与错误检测和校正电路连接的半导体存储器
公开(公告)号：WO1981003567A1
公开(公告)日：1981-12-10
申请号：PCT/US1980000672
申请日：1980-06-02
申请人： MOSTEK CORP , PROEBSTING R
发明人： MOSTEK CORP
IPC分类号： G11C07/00
CPC分类号： G06F11/106 , G11C11/406 , G11C11/4063 , G11C29/48
摘要： A semiconductor dynamic memory circuit (10) includes a memory cell array (38) which includes a plurality of memory cells which are accessed through row and column lines by operation of row and column clock chain signals. A strap (68) is provided to operate the circuit (10) as either a memory which is refreshed according to internally generated addresses or a memory which is refreshed in response to externally supplied memory addresses and is easily incorporated into a memory system which utilizes error detection and correction during the refresh operation. In the absence of the strap (68) a refresh signal (20) refreshes cells of the array (38) in response to the address generated by an internal address counter (82). The circuit (10) accesses a given memory location when an externally supplied address is provided together with a RAS signal (12) and a CAS signal (16). When the strap (68) is incorporated into the circuit (10) the refresh signal (20) applied thereto causes the memory cell array (38) to be refreshed at the externally supplied address. The data within the memory cell array (38) is accessed in response to an externally supplied memory address, the RAS signal (12) and the CAS signal (16). The CAS signal (16) is inhibited in the absence of the RAS signal (12). The circuit (10) is used within a memory array (102) for reading out stored data together with error correcting bits while at the same time refreshing all of the memory circuits in the memory (102). An error detecting and correcting circuit (160) is provided to evaluate the data read out from the memory circuits and to provide a corrected data pattern when erroneous bits are detected.
摘要翻译：半导体动态存储器电路（10）包括存储单元阵列（38），其包括通过行和列时钟链信号的操作通过行和列线访问的多个存储单元。提供带（68）以将电路（10）操作为根据内部生成的地址刷新的存储器或响应于外部提供的存储器地址而刷新的存储器，并且容易地并入到利用错误的存储器系统中在刷新操作期间的检测和校正。在没有带（68）的情况下，刷新信号（20）响应于由内部地址计数器（82）产生的地址刷新阵列（38）的单元。当外部提供的地址与RAS信号（12）和CAS信号（16）一起提供时，电路（10）访问给定的存储器位置。当带（68）被并入到电路（10）中时，施加到其上的刷新信号（20）使得存储单元阵列（38）在外部提供的地址处被刷新。响应于外部提供的存储器地址RAS信号（12）和CAS信号（16）来访问存储单元阵列（38）内的数据。在没有RAS信号（12）的情况下，CAS信号（16）被禁止。电路（10）用在存储器阵列（102）内，用于读出存储的数据以及纠错位，同时刷新存储器（102）中的所有存储器电路。提供错误检测和校正电路（160）以评估从存储器电路读出的数据，并且当检测到错误位时提供校正的数据模式。

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