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1. 发明申请

WO2013138199A1 NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB 审中-公开
标题翻译：具有读取过程的非易失性存储，减少了干扰
公开(公告)号：WO2013138199A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/029991
申请日：2013-03-08
申请人： SANDISK TECHNOLOGIES, INC. , LEI, Bo , WAN, Jun , PAN, Feng
发明人： LEI, Bo , WAN, Jun , PAN, Feng
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427
摘要： A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.
摘要翻译：用于从非易失性存储器读取数据的装置和处理包括将读取的比较信号应用于NAND串的所选择的数据存储单元，将第一组一个或多个读取通过电压施加到未读选择数据存储单元的两端 NAND串，并且将第二组一个或多个读取通过电压施加到NAND串的两端和所选数据存储单元的两侧之间的未选择的数据存储单元。第一组一个或多个读通道电压都高于一个或多个读通道电压的第一组。

2. 发明申请

WO2008036609A2 IMPLEMENTATION OF OUTPUT FLOATING SCHEME FOR HV CHARGE PUMPS 审中-公开
标题翻译：高压充电泵输出浮动方案的实现
公开(公告)号：WO2008036609A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/078667
申请日：2007-09-17
申请人： SANDISK CORPORATION , GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
发明人： GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
CPC分类号： G11C16/30 , G11C5/145
摘要： According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.
摘要翻译：根据本发明的不同实施例，描述了用于管理具有高电压电荷泵和相关联的调节器的非易失性存储器系统中的电荷泵中的功率的各种方法，设备和系统。一种方法包括以下操作：接收对应于操作的操作命令，将电荷泵输出电压上升到期望的输出电压，当输出电压近似为补偿电荷的期望输出电压时关闭调节器和电荷泵通过打开电荷泵并将泵时钟速率设置为较慢的时钟速率来共享，以避免在执行操作时通过电荷泵超出期望的输出电压，并且通过接通调节器来补偿结泄漏并且电荷泵，直到电荷泵输出电压是所需的输出电压。

3. 发明申请

WO2008024822A3 APPARATUS AND METHOD OF SYNCHRONIZING DISTRIBUTION OF PACKET SERVICES ACROSS A DISTRIBUTED NETWORK 审中-公开
公开(公告)号：WO2008024822A3
公开(公告)日：2008-02-28
申请号：PCT/US2007/076489
申请日：2007-08-22
申请人： BRILLIANT TELECOMMUNICATIONS, INC. , BARRY, Charles, F. , PARKER, Reed, A. , SHEN, Tian , PAN, Feng, F. , SUBRAMANIAN, Meenakshi, S.
发明人： BARRY, Charles, F. , PARKER, Reed, A. , SHEN, Tian , PAN, Feng, F. , SUBRAMANIAN, Meenakshi, S.
IPC分类号： H04J3/06
摘要： An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.

4. 发明申请

WO2003067597A3 IMPLEMENTATION OF AN INHIBIT DURING SOFT PROGRAMMING TO TIGHTEN AN ERASE VOLTAGE DISTRIBUTION 审中-公开
公开(公告)号：WO2003067597A3
公开(公告)日：2003-08-14
申请号：PCT/US2003/003710
申请日：2003-02-06
申请人： SANDISK CORPORATION , PAN, Feng , YU,Tat-Kwan, Edgar
发明人： PAN, Feng , YU,Tat-Kwan, Edgar
IPC分类号： G11C16/34
摘要： Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.

5. 发明申请

WO9939303A9 METHOD AND SYSTEM FOR COMPUTING 8X8 DCT/IDCT AND A VLSI IMPLEMENTATION 审中-公开
标题翻译：用于计算8X8 DCT / IDCT和VLSI实现的方法和系统
公开(公告)号：WO9939303A9
公开(公告)日：1999-10-07
申请号：PCT/US9902186
申请日：1999-02-02
申请人： UNIV PENNSYLVANIA , PAN FENG
发明人： PAN FENG
IPC分类号： G06F17/14 , G06K9/36 , G06K9/46
CPC分类号： G06F17/147
摘要： A method and system for computing 2-D DCT/IDCT which is easy to omplement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8x8 DCT/IDCT is computed through four 4x4 matrix multiplication sub-blocks (1320, 1330, 1340, 1350). Each sub-block is half the size of the original 8x8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.
摘要翻译：描述了一种用于计算2D-DCT / IDCT的方法和系统，其易于利用VLSI技术来实现，以实现高吞吐量以实时满足高清晰度视频处理的要求。使用直接的2-D矩阵因式分解方法来计算2-D DCT / IDCT。通过四个4×4矩阵乘法子块（1320,1330,1340,1350）计算8×8 DCT / IDCT。每个子块的大小是原始8x8尺寸的一半，因此需要较少数量的乘法。此外，每个子块可以通过局部互连独立实现，从而可以利用并行性，并且可以实现更高的DCT / IDCT吞吐量。

6. 发明申请

WO2012044424A1 HIGH VOLTAGE SWITCH SUITABLE FOR USE IN FLASH MEMORY 审中-公开
标题翻译：高电压开关适用于闪存存储器
公开(公告)号：WO2012044424A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/049418
申请日：2011-08-26
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan Hoang , PAN, Feng
发明人： HUYNH, Jonathan Hoang , PAN, Feng
IPC分类号： G11C8/08 , G11C16/08 , H03K17/06
CPC分类号： G11C16/08 , G11C8/08 , H03K17/063
摘要： A high voltage switch is presented that, rather than relying upon a charge pump to boost the voltage applied to the switches gate in order to compensate for the switch's threshold voltage, a combination of high voltage devices to eliminate the threshold voltage from the switch. This will save on the needed circuit area and reduce the current and, consequently, power consumption. In the exemplary embodiment, the switch circuit passes an input voltage from an input node to an output node in response to an enable signal. The switch includes a level shifter connected to the input node and is connected to receive the enable signal to provide the input voltage as output when the enable signal is asserted. The circuit also includes a first depletion type NMOS transistor that is connected between the input node and a first intermediate node and having a gate connected to receive the output of the level shifter, and a PMOS transistor that is connected between the first intermediate node and the output node and having a gate connected to receive an inverted form of the enable signal.
摘要翻译：提出了一种高压开关，其不是依赖于电荷泵来升高施加到开关栅极的电压，以便补偿开关的阈值电压，高电压装置的组合以消除来自开关的阈值电压。这将节省所需的电路面积，并减少电流，从而降低功耗。在示例性实施例中，响应于使能信号，开关电路将输入电压从输入节点传递到输出节点。开关包括连接到输入节点的电平移位器，并连接以接收使能信号，以在使能信号被断言时提供输入电压作为输出。电路还包括第一耗尽型NMOS晶体管，其连接在输入节点和第一中间节点之间，并且具有连接以接收电平移位器的输出的栅极，以及连接在第一中间节点和第二中间节点之间的PMOS晶体管输出节点并且具有连接的栅极以接收使能信号的反相形式。

7. 发明申请

WO2012044418A1 LEVEL SHIFTER WITH SHOOT-THROUGH CURRENT ISOLATION 审中-公开
标题翻译：水平切换器，具有穿孔电流隔离
公开(公告)号：WO2012044418A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/049109
申请日：2011-08-25
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan, Hoang , PAN, Feng , NGUYEN, Qui, Vi , PHAM, Trung
发明人： HUYNH, Jonathan, Hoang , PAN, Feng , NGUYEN, Qui, Vi , PHAM, Trung
IPC分类号： G11C16/08 , G11C16/30 , G11C5/14 , G11C8/08
CPC分类号： G11C16/08 , G11C16/30 , H03K19/0013 , H03K19/018521
摘要： A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit includes a depletion type NMOS transistor, having a gate connected to the output node, and a PMOS transistor, having a gate connected to the first enable signal. It also includes a first resistive element that is distinct from the NMOS and PMOS transistors. The NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, with the NMOS transistor being connected to the first node. The level shifter further includes a discharge circuit connected to the second node and to receive a second enable signal. The second enable signal is asserted when the first enable signal is de-asserted and is asserted when the first enable signal is de-asserted, and the discharge circuit connects the second node to the low voltage value when the second enable signal is asserted and isolates the second node from ground when the second enable signal is de-asserted.
摘要翻译：提出了适用于直流电流隔离的高电压应用的电平移位电路。电平移位器接收第一使能信号并在第一节点处接收输入电压，并在第二节点处提供输出电压。响应于第一使能信号被断言，电路提供来自输入电压的输出电压，并且当第一使能信号被解除置位时，将输出节点设置为低电压值。电平移位电路包括具有连接到输出节点的栅极的耗尽型NMOS晶体管和具有连接到第一使能信号的栅极的PMOS晶体管。它还包括与NMOS和PMOS晶体管不同的第一电阻元件。 NMOS晶体管，PMOS晶体管和第一电阻元件串联连接在第一和第二节点之间，NMOS晶体管连接到第一节点。电平移位器还包括连接到第二节点并且接收第二使能信号的放电电路。当第一使能信号被解除置位时，第二使能信号被置位，并且当第一使能信号被断言时被断言，并且当第二使能信号被断言时，放电电路将第二节点连接到低电压值当第二使能信号被取消断言时，来自接地的第二节点。

8. 发明申请

WO2009076277A1 LOW VOLTAGE CHARGE PUMP WITH REGULATION 审中-公开
标题翻译：低压充电泵与调节
公开(公告)号：WO2009076277A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/085827
申请日：2008-12-08
申请人： SANDISK CORPORATION , PAN, Feng , HUYNH, Jonathan H. , NGUYEN, Qui Vi
发明人： PAN, Feng , HUYNH, Jonathan H. , NGUYEN, Qui Vi
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： Techniques of providing a low output voltage, high current capability charge pump are given. The charge pump has multiple capacitors along with switching circuitry. In an initialization phase, the first plate of each of the capacitors is connected to receive a regulator voltage and the second plate of each capacitor is connected to ground. In a transfer phase, the capacitors are connected in series, where, for each capacitor after the first, the second plate is connected to the first plate of the preceding capacitor in the series. The output voltage of the pump is from the first plate of the last capacitor in the series. Regulation circuitry generates the regulator voltage from a reference voltage to have a value responsive to the output voltage level of the pump.
摘要翻译：给出了提供低输出电压，高电流能力的电荷泵的技术。电荷泵具有多个电容器以及开关电路。在初始化阶段，每个电容器的第一板被连接以接收稳压器电压，并且每个电容器的第二板连接到地。在转移阶段，电容器串联连接，其中，对于每个电容器，在第一个电容器之后，第二个板件被连接到串联的前一个电容器的第一个板上。泵的输出电压来自串联的最后一个电容器的第一个板。调节电路从参考电压产生调节器电压，以响应于泵的输出电压电平。

9. 发明申请

WO2008083292A1 GENERATION OF ANALOG VOLTAGE USING SELF-BIASED CAPACITIVE FEEDBACK STAGE 审中-公开
标题翻译：使用自偏置电容反馈阶段产生模拟电压
公开(公告)号：WO2008083292A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/089072
申请日：2007-12-28
申请人： SANDISK CORPORATION , PAN, Feng
发明人： PAN, Feng
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C5/147
摘要： Analog voltage drain with reduced current drain is achieved by a new capacitive-divided feedback architecture. During the operational phase an op amp monitors a capacitively-divided fraction of the output voltage, and drives a current sink or source accordingly; during an initial phase the output is forced to the correct value by a different circuit, while the opamp is connected to self-tune itself in a way which removes DC offset effects.
摘要翻译：具有减少电流消耗的模拟电压消耗通过新的电容分压反馈架构实现。在运行阶段，运算放大器监视输出电压的电容分数，相应地驱动电流接收器或源; 在初始阶段，输出通过不同的电路被强制为正确的值，而运算放大器被连接到以自动调整自身的方式来消除DC偏移效应。

10. 发明申请

WO2008016571A1 HYBRID CHARGE PUMP REGULATION WITH SELECTABLE FEEDBACK CIRCUITS 审中-公开
标题翻译：混合充电泵调节与可选择的反馈电路
公开(公告)号：WO2008016571A1
公开(公告)日：2008-02-07
申请号：PCT/US2007/017043
申请日：2007-07-30
申请人： SANDISK CORPORATION , PAN, Feng
发明人： PAN, Feng
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/145
摘要： Techniques for reliably and efficiently generating an output voltage (VOLT) for use within an electronic device, such as a memory system, are disclosed. A voltage generation circuit (502) generates the output voltage. The voltage generation circuit includes regulation circuitry that controls regulation of the output voltage to maintain the output voltage at a substantially constant level. According to one aspect, regulation is provided through use of different feedback circuits. By selectively disabling one (503) of the feedback circuits, power consumption can be reduced and the other of the feedback circuits (504) can support the continued regulation of the output voltage. The voltage generation circuit is therefore able to operate in an accurate, stable and power efficient manner.
摘要翻译：公开了用于可靠且有效地产生用于诸如存储器系统的电子设备内的输出电压（VOLT）的技术。电压产生电路（502）产生输出电压。电压产生电路包括调节电路，其控制输出电压的调节以将输出电压维持在基本上恒定的水平。根据一个方面，通过使用不同的反馈电路来提供调节。通过选择性地禁用一个（503）反馈电路，可以降低功耗，并且反馈电路（504）中的另一个可以支持输出电压的持续调节。因此，电压产生电路能够以精确，稳定和功率效率的方式工作。

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