专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2016003820A3 SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
标题翻译：用于宽泛操作说明的系统和方法
公开(公告)号：WO2016003820A3
公开(公告)日：2016-03-17
申请号：PCT/US2015038078
申请日：2015-06-26
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
摘要： Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
摘要翻译：公开了可扩展地广泛的操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序并在宽缓存中使用操作数。

2. 发明申请

WO0023875A8 SYSTEM WITH WIDE OPERAND ARCHITECTURE, AND METHOD 审中-公开
标题翻译：具有宽操作体系结构的系统和方法
公开(公告)号：WO0023875A8
公开(公告)日：2001-06-07
申请号：PCT/US9919342
申请日：1999-08-24
申请人： MICROUNITY SYSTEMS ENG , HANSEN CRAIG , MOUSSOURIS JOHN
发明人： HANSEN CRAIG , MOUSSOURIS JOHN
IPC分类号： G06F9/38 , G06F7/38 , G06F7/48 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/318 , G06F9/34
CPC分类号： G06F9/30014 , G06F7/483 , G06F7/4991 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/30112 , G06F9/30167 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently for four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).
摘要翻译：具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。访问单元独立地为四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令和访问存储器来执行每个计算控制流程。这些访问单元还提供广泛的说明符，用于广泛的操作数指令。这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。

3. 发明申请

WO9427204A3 BIAS VOLTAGE DISTRIBUTION SYSTEM 审中-公开
标题翻译：偏置电压分配系统
公开(公告)号：WO9427204A3
公开(公告)日：1995-01-19
申请号：PCT/US9404614
申请日：1994-04-28
申请人： MICROUNITY SYSTEMS ENG
发明人： HERNDON WILLIAM H
IPC分类号： G05F3/24 , H03K19/00 , H03K19/086 , G05F1/577
CPC分类号： G05F3/24
摘要： The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.
摘要翻译：一种偏置发生和分配系统，其中在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分配到MOS负载器件，MOS负载网络，其他偏置电压转换中心和逻辑电路。该系统产生第一偏置电压，其提供用于偏置MOS负载装置和并联MOS负载网络的温度补偿电压。第一偏置电压发生器包括参考MOS负载装置或参考并联MOS负载网络，其确定第一偏置电压的值。参考MOS负载网络包括响应于第一组控制信号的交换网络。可以调整第一组控制信号以改变第一偏置电压的值以补偿过程变化。第一个偏置电压分配到远程单负载MOS器件或远程并行MOS负载网络。远程负载网络还包括响应于第二组控制信号的交换网络。可以改变第二组控制信号以根据第一偏置电压的值确定远程MOS负载网络的电阻率。该系统还产生第二温度补偿偏置电压，其与第一偏置电压一起使用以偏置远程偏置转换电路。远程转换电路产生与第一偏置电压一起被利用以偏置远程逻辑门的第三偏置电压。第一偏置电压偏置逻辑门的MOS电阻负载，第三偏置电压偏置逻辑门的MOS电流器件。第二偏置电压发生器和远程转换电路由可控开关网络实现，从而可以执行逻辑门的电流和逻辑摆幅调整。

4. 发明申请

WO2016003820A2 SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
标题翻译：用于扩展操作和指令的系统和方法
公开(公告)号：WO2016003820A2
公开(公告)日：2016-01-07
申请号：PCT/US2015038078
申请日：2015-06-26
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
摘要： Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
摘要翻译：公开了可扩展的宽操作，其中操作数比处理器和存储器之间的数据路径宽，用于执行指令。可扩展的宽操作数减少了在执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统和负载中的操作序列并在宽缓存中使用操作数。

5. 发明申请

WO9707451A3 METHOD AND SYSTEM FOR IMPLEMENTING DATA MANIPULATION OPERATIONS 审中-公开
标题翻译：执行数据操作操作的方法和系统
公开(公告)号：WO9707451A3
公开(公告)日：1997-04-10
申请号：PCT/US9613195
申请日：1996-08-14
申请人： MICROUNITY SYSTEMS ENG , KARZES THOMAS J , HANSEN CRAIG C , MASSALIN HENRY
发明人： KARZES THOMAS J , HANSEN CRAIG C , MASSALIN HENRY
IPC分类号： G06F7/76 , G06F9/30 , G06F9/308 , G06F9/315 , G06F7/00
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30018 , G06F9/30025 , G06F9/30032
摘要： A method and system for performing arbitrary permutations of sequences of elements. In the general case, the method of the present invention processes the elements to be permuted as a multi-dimensional array, where each element in the array corresponds to one of the elments to be permuted. The permutation is achieved by performing a sequence of sets of permutations, where each set of permutations in the sequence independently permutes the elements within each one-dimensional slice through the array, along some particular dimension of the array. The total number of sets of permutations, or stages, is one less than twice the number of dimensions in the array. An extension to the general method allows some extensions of permutations which involve the copying of individual elements. A system based on the extended general method implements a large class of operations which involve copying and/or permuting elements, where the sequence of elements is a word of data and the elements are bits of data. An efficient control structure for the system permits control signals to be shared across slices of the array. A version of the system based on a two-dimensional array includes three multiplex stages, where the first stage multiplexes along the rows, the second stage multiplexes along the columns, and the third stage multiplexes across the rows once again. Several classes of computer instructions which generally involve the copying and/or permuting of data are also described.

6. 发明申请

WO2005008410A2 PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS 审中-公开
标题翻译：具有广泛操作的可编程处理器和方法
公开(公告)号：WO2005008410A2
公开(公告)日：2005-01-27
申请号：PCT/US2004022126
申请日：2004-07-12
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F20060101 , G06F12/00 , G06F17/50 , G06F
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4425 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展为大于通用寄存器或数据路径宽度的宽度来改善处理器的性能。本发明通过使用通用寄存器的内容来提供实质上大于处理器的数据路径宽度的操作数，以指定可以读取或写入多个数据路径宽度的存储器地址，以及操作数的大小和形状。另外，描述了用于实现这些指令的若干指令和装置，如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优势。

7. 发明申请

WO9714084A3 VIRTUAL MEMORY SYSTEM WITH LOCAL AND GLOBAL VIRTUAL ADDRESS TRANSLATION 审中-公开
标题翻译：具有本地和全球虚拟地址翻译的虚拟内存系统
公开(公告)号：WO9714084A3
公开(公告)日：1997-10-23
申请号：PCT/US9616297
申请日：1996-10-10
申请人： MICROUNITY SYSTEMS ENG , HANSEN CRAIG C
发明人： HANSEN CRAIG C
IPC分类号： G06F12/02 , G06F12/10 , G06F12/14 , G06F
CPC分类号： G06F12/0284 , G06F12/1045 , G06F12/1491
摘要： A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Local-to-global virtual translation is performed by either mapping local virtual addresses to a single global virtual address space or to multiple global virtual address spaces. The local-to-global virtual translator includes a cell which corresponds to each local address space for performing the translations. Separate cache and tag structures are employed for handling data and instruction memory accesses. The cache can be configured into a buffer portion or a cache portion for faster cache accesses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit, cache miss, or buffer access occurs during a given data or instruction access. Memory area privilege protection is also achieved by employing a gateway instruction which generates an address to access a gateway storage area.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式