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1. 发明申请

WO8700674A3 WAFER-SCALE INTEGRATED CIRCUIT MEMORY 审中-公开
标题翻译：超大规模集成电路存储器
公开(公告)号：WO8700674A3
公开(公告)日：1987-03-26
申请号：PCT/GB8600400
申请日：1986-07-11
申请人： ANAMARTIC LTD , BRENT MICHAEL , MACDONALD NEAL
发明人： BRENT MICHAEL , MACDONALD NEAL
IPC分类号： G06F11/20 , G11C7/00 , G11C7/22 , G11C8/00 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/00
CPC分类号： G11C8/00 , G11C7/00 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/006
摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.

2. 发明申请

WO8703716A3 FAULT TOLERANT MEMORY SYSTEM 审中-公开
标题翻译：容错记忆系统
公开(公告)号：WO8703716A3
公开(公告)日：1987-07-16
申请号：PCT/GB8600760
申请日：1986-12-12
申请人： ANAMARTIC LTD , MACDONALD NEAL
发明人： MACDONALD NEAL
IPC分类号： G06F12/16 , G06F11/00 , G06F11/16 , G11C29/00
CPC分类号： G11C29/70 , G11C29/006 , G11C29/86
摘要： A digital computer (15) can write a block of data to a RAM (10), or read a block therefrom, via a serial/parallel converter (17) which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter (18) clocked by clock pulses WCK. A fault masking circuit (19) enables faulty cells in the RAM (10) to be masked out. Data specific to the RAM (10) causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter (17). These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs (10) served by a single fault masking circuit (19) with tabulated data defining the memory cells to be masked out on a memory by memory basis.

3. 发明申请

WO8702487A3 CONTROL SYSTEM FOR CHAINED CIRCUIT MODULES 审中-公开
标题翻译：链式电路模块控制系统
公开(公告)号：WO8702487A3
公开(公告)日：1987-06-18
申请号：PCT/GB8600601
申请日：1986-10-06
申请人： ANAMARTIC LTD , MACDONALD NEAL
发明人： MACDONALD NEAL
IPC分类号： G11C29/00 , G06F11/20 , G06F15/60
CPC分类号： G11C29/006
摘要： A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent from a terminal (XMIT) to the modules along a transmit path set up by way of module inputs from neighbouring modules and outputs thereto, only one of which is enabled by one of four selection signals. The transmit path normally follows a route through a main chain of modules (M0 to M15), as shown by a full line. However, commands may be sent to nodal modules (M0, M6 and M10) to make alternative direction selections there at, so as to obtain access to modules (M16) etc. in spur chains. Commands are addressed to the modules in accordance with their distances (F) from (XMIT). Spurs may themselves include nodal moduls such as (M17). The normal and alternative direction selections are listed in a stored table which is used by a command unit to access any desired module and then restore the main chain (M0 - M15). In an alternative embodiment, the stored table lists individually for every module the sequence of direction selections needed to obtain access thereto by the shortest route avoiding unusable modules (marked with a cross).
摘要翻译：晶圆级集成电路包括几百个模块，这些模块可以通过从终端（XMIT）沿着通过来自相邻模块的模块输入建立的发送路径向模块发送命令并将其输出到长链中而连接成长链其中之一由四个选择信号之一启用。发送路径通常遵循通过主链模块（M0到M15）的路由，如实线所示。然而，可以将命令发送到节点模块（M0，M6和M10）以在那里进行替代的方向选择，以便获得对短链中的模块（M16）等的访问。根据距离（XMIT）的距离（F）将命令发给模块。马刺本身可能包括节点模块，如（M17）。存储的表格中列出了正常和替代方向选择，命令单元使用该表格存取任何所需的模块，然后恢复主链（M0-M15）。在替代实施例中，所存储的表单独地为每个模块列出需要通过避免不可用模块（用十字标记）的最短路线获得对其的访问所需的方向选择序列。

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