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1. 发明申请

WO1990012399A1 CONTROL SYSTEM FOR AN ARRAY OF CIRCUIT MODULES 审中-公开
标题翻译：电路模块阵列控制系统
公开(公告)号：WO1990012399A1
公开(公告)日：1990-10-18
申请号：PCT/GB1990000539
申请日：1990-04-09
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G11C07/00
CPC分类号： G11C7/22 , G11C8/12 , G11C8/18
摘要： A digital computer can control an array of circuit modules through the use of two sets of pan-array signals, known as R and C. The C lines run vertically and connect to all modules in the same column, and the R lines run horizontally and connect to all chips in the same row of the array. By asserting a particular pair of R and C lines, a specific module can be selected to receive control data from one of these lines. Each module includes a support circuit to latch when R and C are asserted together, and then to route data from one line into a variety of storage registers. A particular example is described that uses the control system as the basis of a data storage and retrieval system.
摘要翻译：数字计算机可以通过使用两组pan-array信号（称为R和C）来控制电路模块阵列.C线垂直运行并连接到同一列中的所有模块，R线水平运行，连接到阵列的同一行中的所有芯片。通过断言特定的一对R和C线，可以选择一个特定的模块来从这些线路之一接收控制数据。每个模块包括一个支持电路，当R和C一起被断言时锁存，然后将数据从一行路由到各种存储寄存器。描述了使用控制系统作为数据存储和检索系统的基础的特定示例。

2. 发明申请

WO1992008193A1 A FAULT TOLERANT DATA STORAGE SYSTEM 审中-公开
标题翻译：一个容错数据存储系统
公开(公告)号：WO1992008193A1
公开(公告)日：1992-05-14
申请号：PCT/GB1991001929
申请日：1991-11-04
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A fault tolerant random access data storage system comprises a plurality of rows of memory chips (31) plus a first spare row of chips (32) and a second spare row of chips (33), each chip comprising an array of memory locations. A controller (25) addresses the chips with the logical addresses of the rows within the arrays being skewed relative to their physical addresses but in a different manner for the different rows of chips, and with the logical addresses of the columns within the arrays being skewed relative to their physical addresses but in a different manner for the different rows of chips. The locations of faults within the chips are recorded so that if a selected array row in a selected chip row (31) is faulty, then a replacement row in the first spare row of chips (32) is selected instead, and if a selected array column in a selected chip row (31) is faulty, then a replacement column in the second spare row of chips (33) is selected instead.
摘要翻译：容错随机存取数据存储系统包括多行存储器芯片（31）加上第一备用行芯片（32）和第二备用行芯片（33），每个芯片包括一组存储器位置。控制器（25）以阵列内的行的逻辑地址相对于它们的物理地址进行寻址，但以不同的方式对于不同行的码片进行寻址，并且阵列内的列的逻辑地址偏斜相对于它们的物理地址，但以不同的方式对于不同行的芯片。记录芯片内的故障位置，使得如果选定的芯片行（31）中选定的阵列行有故障，则替代地选择第一备用行芯片（32）中的替换行，并且如果选择的阵列选择的芯片行（31）中的列是故障的，则替代地选择第二备用行芯片（33）中的替换列。

3. 发明申请

WO1991001023A1 A FAULT TOLERANT DATA STORAGE SYSTEM 审中-公开
标题翻译：一个容错数据存储系统
公开(公告)号：WO1991001023A1
公开(公告)日：1991-01-24
申请号：PCT/GB1990001051
申请日：1990-07-06
申请人： MV LIMITED , MACDONALD, Neal, Hugh
发明人： MV LIMITED
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A fault tolerant data storage system comprises an array of memory chips having a plurality of rows and columns, each row of memory chips CO to CN having a spare chip CS. Each chip comprises an array of memory locations some of which may be faulty. When simultaneously writing or reading data via parallel data lines DO-DN to the respective chips, a map MAP identifies any chip having a fault in the addressed location (e.g. in the addressed column) and connects the data line to a good location in the spare chip. The logical addresses for the chips are skewed differently for each other as compared with their physical addresses, such that there are not coincident faults in the different chips e.g. only a single chip in a row has a fault in the columns being simultaneously addressed in the respective chips of that row.
摘要翻译：容错数据存储系统包括具有多个行和列的存储器芯片阵列，每行存储器芯片CO至CN具有备用芯片CS。每个芯片包括一些存储器位置，其中一些可能是有缺陷的。当通过并行数据线DO-DN将数据同时写入或读取到相应的芯片时，映射MAP识别在寻址位置（例如，寻址列）中具有故障的任何芯片，并将数据线连接到备用的良好位置芯片。与其物理地址相比，芯片的逻辑地址彼此不同，使得不同的芯片中不存在重合故障，例如，只有一行中的单个芯片在该行的各个芯片中同时处理列中的故障。

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