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1. 发明申请

WO2011022080A1 PACKAGING SYSTEM FOR A FLOOR PANEL 审中-公开
标题翻译：一种地板包装系统
公开(公告)号：WO2011022080A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/002319
申请日：2010-08-20
申请人： ARMSTRONG WORLD INDUSTRIES, INC. , BALMER, Richard, H. , DAO, Dung, V. , KNAFELC, Christopher, R. , LEE, Shih, Chung , HARRINGTON, Heath, E. , ANSPACH, Kean, M. , BUCKWALTER, Michael, E. , ESHBACH, John, R., Jr.
发明人： BALMER, Richard, H. , DAO, Dung, V. , KNAFELC, Christopher, R. , LEE, Shih, Chung , HARRINGTON, Heath, E. , ANSPACH, Kean, M. , BUCKWALTER, Michael, E. , ESHBACH, John, R., Jr.
IPC分类号： E04B5/02
CPC分类号： B65D85/62 , B65B11/004 , B65B35/50
摘要： A packaging system and a method of packaging a plurality of floor panels (10) in a box (30) includes floor panels having a top layer (11) and a bottom layer (12). The top layer has a top surface (14) with a visible decorative pattern and a bottom surface (15) adhered to a top surface (18) of the bottom layer such that the bottom layer is offset from the top layer in a direction of length (L1, L2) and width (W1, W2) and a marginal end portion of the top surface of the bottom layer and a marginal end portion of the bottom surface of the top layer is exposed. The floor panels are stacked in the box in pairs (51). Each of the pairs is stacked such that the top surfaces of the top layers of each of the pairs of the floor panels are facing each other.
摘要翻译：包装系统和将多个地板镶板（10）包装在盒（30）中的方法包括具有顶层（11）和底层（12）的地板镶板。顶层具有具有可见装饰图案的顶表面（14）和粘附到底层顶表面（18）的底表面（15），使得底层在长度方向上偏离顶层（L1，L2）和宽度（W1，W2）以及底层顶表面的边缘端部和顶层底面的边缘端部露出。地板镶板成对地堆叠在盒子中（51）。每对成对被堆叠，使得每对地板镶板的顶层的顶表面彼此面对。

2. 发明申请

WO2010068323A1 ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY 审中-公开
标题翻译：自适应删除和软件编程存储器
公开(公告)号：WO2010068323A1
公开(公告)日：2010-06-17
申请号：PCT/US2009/058002
申请日：2009-09-23
申请人： SANDISK CORPORATION , LEE, Shih-Chung , HEMINK, Gerrit, Jan
发明人： LEE, Shih-Chung , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C16/3404
摘要： An erase sequence of a non-volatile storage device includes an erase operation (910) followed by a soft programming operation (930). The erase operation applies one or more erase pulses to the storage elements (920), e.g. via a substrate until an erase level is satisfied (924) The number of erase pulses is tracked and recorded ( (926) as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation (930) applies soft programming pulses (944) to the storage elements until a soft programming verify level is satisfied (950). Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations (946) for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as staring amplitude, step size or pulse duration.
摘要翻译：非易失性存储设备的擦除序列包括随后进行软编程操作的擦除操作（910）（930）。擦除操作将一个或多个擦除脉冲施加到存储元件（920）。通过衬底直到擦除电平满足（924）擦除和记录擦除脉冲数（（926）作为存储设备经历的编程擦除周期数的标记，软编程操作（930）将软编程脉冲（944）应用于存储元件，直到满足软编程验证电平（950）为止，基于擦除脉冲数，通过跳过验证操作（946）来缩短软编程操作时间，作为擦除脉冲数的函数的初始软编程脉冲，此外，可以优化软编程操作的特性，例如振幅，步长或脉冲持续时间。

3. 发明申请

WO2008054986A3 FASTER PROGRAMMING OF HIGHEST MULTI-LEVEL STATE FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：更快地编写非易失性存储器的最高级别状态
公开(公告)号：WO2008054986A3
公开(公告)日：2008-06-12
申请号：PCT/US2007081419
申请日：2007-10-15
申请人： SANDISK CORP , HEMINK GERRIT JAN , LEE SHIH-CHUNG
发明人： HEMINK GERRIT JAN , LEE SHIH-CHUNG
IPC分类号： G11C16/12
CPC分类号： G11C16/12
摘要： A coarse/fine programming technique is used for programming to lower states while using a standard technique (not coarse/fine programming) for programming to the highest state(s). However, when the programming of the lower states is finished, a number of programming pulses are still needed to program the highest state. To improve the programming speed, a bigger step size and longer programming pulse can be used from the moment that the lowest states have been programmed. At the same time, the programming technique for the highest state can be changed to a coarse/fine programming technique.
摘要翻译：在使用标准技术（不是粗/精编程）来编程到最高状态时，粗/精编程技术用于编程以降低状态。然而，当下部状态的编程完成时，仍然需要多个编程脉冲来编程最高状态。为了提高编程速度，从最低状态被编程的时刻起，可以使用更大的步长和更长的编程脉冲。同时，用于最高状态的编程技术可以改变为粗/精编程技术。

4. 发明申请

WO2008054986A2 FASTER PROGRAMMING OF HIGHEST MULTI-LEVEL STATE FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：对非易失性存储器的最高多级状态进行更快速的编程
公开(公告)号：WO2008054986A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/081419
申请日：2007-10-15
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-chung
发明人： HEMINK, Gerrit, Jan , LEE, Shih-chung
IPC分类号： G11C16/12
CPC分类号： G11C16/12
摘要： A coarse/fine programming technique is used for programming to lower states while using a standard technique (not coarse/fine programming) for programming to the highest state(s). However, when the programming of the lower states is finished, a number of programming pulses are still needed to program the highest state. To improve the programming speed, a bigger step size and longer programming pulse can be used from the moment that the lowest states have been programmed. At the same time, the programming technique for the highest state can be changed to a coarse/fine programming technique.
摘要翻译：粗略/精细的编程技术用于编程降低状态，同时使用标准技术（不粗略/精细编程）编程到最高状态。但是，当较低状态的编程完成时，仍然需要多个编程脉冲来编程最高状态。为了提高编程速度，从编程最低状态开始，可以使用更大的步长和更长的编程脉冲。同时，用于最高状态的编程技术可以改变为粗略/精细编程技术。

5. 发明申请

WO2013147936A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMNMING 审中-公开
标题翻译：在编程期间选定的字线相关选择门限扩展区域电压
公开(公告)号：WO2013147936A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066610
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
发明人： LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

6. 发明申请

WO2011022078A1 METHOD OF MAKING A FLOOR PANEL 审中-公开
标题翻译：制作地板面板的方法
公开(公告)号：WO2011022078A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/002312
申请日：2010-08-20
申请人： ARMSTRONG WORLD INDUSTRIES, INC. , BALMER, Richard, H. , DAO, Dung, V. , ESHBACH, John, R. , LEE, Shih, Chung , HARRINGTON, Heath, E. , BUCKWALTER, Michael, E. , ANSPACH, Kean, M.
发明人： BALMER, Richard, H. , DAO, Dung, V. , ESHBACH, John, R. , LEE, Shih, Chung , HARRINGTON, Heath, E. , BUCKWALTER, Michael, E. , ANSPACH, Kean, M.
IPC分类号： E04C2/00
CPC分类号： B32B37/18 , B32B37/1284 , B32B38/0004 , B32B2037/268 , B32B2309/105 , B32B2419/04 , B32B2607/00 , E04F15/02155 , E04F15/10 , E04F2201/07 , E04F2203/06 , Y10T156/10 , Y10T156/1085 , Y10T156/1087
摘要： A method of making a floor panel (10) includes the steps of: providing an adhesive (25) on a release member (13); laminating or marrying the release member (13) to a bottom layer (12) such that the adhesive (25) is between the release member (13) and the bottom layer (12); removing a portion of the release member (13) to expose an area of the adhesive (25); and adhering a top layer (11) to the area such that the top layer (11) is offset with respect to the bottom layer (12) in a direction of length (L2) and width (W2) and a marginal end portion of a top surface (18) of the bottom layer (12) and a marginal end portion of the bottom surface (15) of the top layer (11) is exposed.
摘要翻译：制造地板（10）的方法包括以下步骤：在释放构件（13）上提供粘合剂（25）; 将释放构件（13）层压或结合到底层（12），使得粘合剂（25）在释放构件（13）和底层（12）之间; 移除所述释放构件（13）的一部分以暴露所述粘合剂（25）的区域; 并且将顶层（11）粘附到所述区域，使得顶层（11）在长度（L2）和宽度（W2）的方向上相对于底层（12）偏移，并且边缘端部底层（12）的顶表面（18）和顶层（11）的底表面（15）的边缘端部暴露。

7. 发明申请

WO2009148906A1 ERASE-VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储的擦除验证过程
公开(公告)号：WO2009148906A1
公开(公告)日：2009-12-10
申请号：PCT/US2009/045358
申请日：2009-05-28
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
发明人： HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
IPC分类号： G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non- volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non- volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功地擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

8. 发明申请

WO2008039667A3 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少非挥发性储存中的程序干扰
公开(公告)号：WO2008039667A3
公开(公告)日：2008-06-05
申请号：PCT/US2007078842
申请日：2007-09-19
申请人： SANDISK CORP , HEMINK GERRIT JAN , LEE SHIH-CHUNG
发明人： HEMINK GERRIT JAN , LEE SHIH-CHUNG
IPC分类号： G11C16/10 , G11C16/04 , G11C16/12 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统以通过在可以被部分编程的连接的非易失性存储元件的一个或多个字线上施加更高的升压电压来减少编程干扰的方式进行编程。

9. 发明申请

WO2008039667A2 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少非易失性存储中的程序干扰
公开(公告)号：WO2008039667A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/078842
申请日：2007-09-19
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-chung
发明人： HEMINK, Gerrit, Jan , LEE, Shih-chung
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统以这样的方式编程：通过在连接到可被部分编程的非易失性存储元件的一条或多条字线上施加较高升压电压来减少编程干扰。

10. 发明申请

WO2007112213A3 PROGRAM TIME ADJUSTMENT AS FUNCTION OF PROGRAM VOLTAGE FOR IMPROVED PROGRAMMING SPEED 审中-公开
公开(公告)号：WO2007112213A3
公开(公告)日：2007-10-04
申请号：PCT/US2007/064064
申请日：2007-03-15
申请人： SANDISK CORPORATION , LEE, Shih-Chung , MIWA, Toru
发明人： LEE, Shih-Chung , MIWA, Toru
IPC分类号： G11C16/34
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of iterative pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.

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