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1. 发明申请

WO2008085574A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 审中-公开
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：WO2008085574A1
公开(公告)日：2008-07-17
申请号：PCT/US2007/081377
申请日：2007-10-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PAGETTE, Francois , LAVOIE, Christian , TOPOL, Anna, W.
发明人： PAGETTE, Francois , LAVOIE, Christian , TOPOL, Anna, W.
IPC分类号： H01L29/737
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a suicided sub-collector next to the first sub-collector; and a suicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the suicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的自吸式副集电极; 以及与所述第二子集电器接触的自杀式到达通道，其中所述第一和第二子集电器和所述辅助到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

2. 发明申请

WO2007044305A2 PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT 审中-公开
标题翻译：包括用于障碍物增强的氧/氮过渡区的种植层
公开(公告)号：WO2007044305A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/038475
申请日：2006-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
发明人： YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
IPC分类号： H01L23/58
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76856 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.
摘要翻译：提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。优选地，互连导电材料是Cu或AlCu。在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

3. 发明申请

WO2006060574A2 METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 审中-公开
标题翻译：在CMOS器件中形成自对准的双完全硅化物门的方法
公开(公告)号：WO2006060574A2
公开(公告)日：2006-06-08
申请号：PCT/US2005/043473
申请日：2005-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
发明人： FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270），第一阱区（253）中的第一源极/漏极硅化物区域（266）和与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）。在所述半导体衬底（252）中形成具有第二阱区（254）的第二类型半导体器件（280），所述第二阱区（254）中的第二源极/漏极硅化物区域（256）和第二类型栅极（258））与第二源极/漏极硅化物区域（256）隔离; 选择性地在所述第二类型半导体器件（280）上形成第一金属层（218）; 仅在第二类型栅极（258）上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

4. 发明申请

WO2006015912A1 MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS 审中-公开
标题翻译：具有多个自对准硅化物接触的MOSFET结构
公开(公告)号：WO2006015912A1
公开(公告)日：2006-02-16
申请号：PCT/EP2005/053082
申请日：2005-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHAN, Kevin , LAVOIE, Christian , RIM, Kern
发明人： CHAN, Kevin , LAVOIE, Christian , RIM, Kern
IPC分类号： H01L21/336
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor (14) having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide (32) having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide (30) located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管（14），其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物（32），其具有基本上对准所述至少一个金属氧化物半导体场效应晶体管的栅极边缘的边缘; 以及位于第一内部硅化物附近的第二外部硅化物（30）。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

5. 发明申请

WO2011056313A3 STRUCTURE AND METHOD TO FORM A THERMALLY STALE SILICIDE IN NARROW DIMENSION GATE STACKS 审中-公开
标题翻译：狭窄尺寸栅堆叠中形成热层硅化物的结构和方法
公开(公告)号：WO2011056313A3
公开(公告)日：2011-08-18
申请号：PCT/US2010049901
申请日：2010-09-23
申请人： IBM , OZCAN AHMET S , LAVOIE CHRISTIAN , DOMENICUCCI ANTHONY G
发明人： OZCAN AHMET S , LAVOIE CHRISTIAN , DOMENICUCCI ANTHONY G
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/66507 , H01L29/6653 , H01L29/6659
摘要： An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250°C to 450°C. Subsequently, a segregation anneal at a temperature in the range 450°C to 550°C. The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.
摘要翻译：提供集成电路，其包括具有小于或等于65nm的宽度的窄栅极叠层，包括硅化物区域，该硅化物区域包括在远离硅化物顶表面的硅化物区域中偏析的Pt以及朝向由在栅极导体的侧壁上的间隔物的下拉高度。在一个优选实施例中，在形成硅化物之前将隔离物拉下。该硅化物首先通过形成退火在250℃至450℃的温度下形成。随后，在450℃至550℃的温度下进行偏析退火。沿着硅化物层的垂直长度的Pt的分布在分离区域内具有峰值Pt浓度，并且分离的Pt区域具有在峰值Pt浓度的一半处的宽度，其小于顶部表面之间的距离的50％的硅化层和下拉间隔物高度。

6. 发明申请

WO2006060575A2 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：WO2006060575A2
公开(公告)日：2006-06-08
申请号：PCT/US2005043474
申请日：2005-12-01
申请人： IBM , CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , ELLIS-MONAGHAN JOHN J , FANG SUNFEI , LAVOIE CHRISTIAN , LUO ZHIJIONG , NAKOS JAMES S , STEEGEN AN L , WANN CLEMENT H
发明人： CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , ELLIS-MONAGHAN JOHN J , FANG SUNFEI , LAVOIE CHRISTIAN , LUO ZHIJIONG , NAKOS JAMES S , STEEGEN AN L , WANN CLEMENT H
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

7. 发明申请

WO2007133356A1 METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS 审中-公开
标题翻译：形成自对准金属硅化物接触的方法
公开(公告)号：WO2007133356A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/008798
申请日：2007-04-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FANG, Sunfei , KNARR, Randolph, F. , KRISHNAN, Mahadevaiyer , LAVOIE, Christian , MO, Renee, T. , PRANATHARTHIHARAN, Balasubramanian , STRANE, Jay, W.
发明人： FANG, Sunfei , KNARR, Randolph, F. , KRISHNAN, Mahadevaiyer , LAVOIE, Christian , MO, Renee, T. , PRANATHARTHIHARAN, Balasubramanian , STRANE, Jay, W.
IPC分类号： H01L21/44 , C23F1/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： A method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region is disclosed. Each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region, is essentially free of metal and metal silicide. Nickel or nickel alloy deposition is followed by low-temperature annealing, nickel etching, high-temperature annealing, and aqua regla etching.
摘要翻译：公开了一种用于在通过暴露的电介质区域彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的硅化镍和硅化铂，并且暴露的电介质区域基本上不含金属和金属硅化物。镍或镍合金沉积之后是低温退火，镍蚀刻，高温退火和水蚀刻蚀刻。

8. 发明申请

WO2006060574A3 METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 审中-公开
标题翻译：在CMOS器件中形成自对准双全硅化栅极的方法
公开(公告)号：WO2006060574A3
公开(公告)日：2006-07-20
申请号：PCT/US2005043473
申请日：2005-12-01
申请人： IBM , FANG SUNFEI , CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , LAVOIE CHRISTIAN , WANN CLEMENT H
发明人： FANG SUNFEI , CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , LAVOIE CHRISTIAN , WANN CLEMENT H
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅极的方法，其中该方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270），第一阱区（253）中的第一源极/漏极硅化物区域（266）以及与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）; 形成具有半导体衬底（252）中的第二阱区（254），第二阱区（254）中的第二源极/漏极硅化物区（256）和第二类型栅极（258）的第二类型半导体器件）与第二源极/漏极硅化物区域（256）隔离; 在所述第二类型半导体器件（280）上方选择性地形成第一金属层（218）; 仅在所述第二类型栅极（258）上执行第一全硅化物（FUSI）栅极形成; 在第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

9. 发明申请

WO2006072538A1 SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS 审中-公开
标题翻译： NANOTUBE / NANOWIRE FET的自对准工艺
公开(公告)号：WO2006072538A1
公开(公告)日：2006-07-13
申请号：PCT/EP2005/056746
申请日：2005-12-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , AVOURIS, Phaedon , CARRUTHERS, Roy , CHEN, Jia , DETAVERNIER, Christophe , LAVOIE, Christian , WONG, Hon-sum Philip
发明人： AVOURIS, Phaedon , CARRUTHERS, Roy , CHEN, Jia , DETAVERNIER, Christophe , LAVOIE, Christian , WONG, Hon-sum Philip
IPC分类号： H01L51/00
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A semiconductor structure comprising: a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure; and a metal carbide contact located on a surface of said substrate that is aligned to an edge of said layer of at least one one-dimensional nanostructure.
摘要翻译：一种半导体结构，包括：衬底，其包括位于其上的至少一个栅极区域，所述至少一个栅极区域包括至少一个一维纳米结构层; 以及金属碳化物接触件，位于所述衬底的与至少一个一维纳米结构的所述层的边缘对准的表面上。

10. 发明申请

WO2012109079A1 A METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS 审中-公开
标题翻译：一种使用过程的方法，并扩大了具有极小尺寸结构的硅酮，锗化物或锗氰酸酯形成的工艺窗口
公开(公告)号：WO2012109079A1
公开(公告)日：2012-08-16
申请号：PCT/US2012/023569
申请日：2012-02-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FLETCHER, Benjamin Luke , LAVOIE, Christian , MAURER, Siegfried Lutz , ZHANG, Zhen
发明人： FLETCHER, Benjamin Luke , LAVOIE, Christian , MAURER, Siegfried Lutz , ZHANG, Zhen
IPC分类号： H01L21/44
CPC分类号： B82Y40/00 , B82Y10/00 , H01L29/0673 , H01L29/16 , H01L29/66469 , H01L29/775
摘要： Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.
摘要翻译：提供了极小结构中硅化物，锗化锗或锗硅化物形成技术。一方面，提供了在具有极小尺寸的三维硅，锗或硅锗结构中形成硅化物，锗化锗或锗硅化物的方法。该方法包括以下步骤。将至少一个元件植入结构中。至少一种金属沉积在结构上。将该结构退火以将硅，锗或硅锗内的金属分散以形成硅化物，锗化锗或锗硅化物，其中所述植入元件用于防止硅化物，锗化物或锗硅化物的形态降解。植入元件可以包括碳，氟和硅中的至少一种。

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