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1. 发明申请

WO2014039210A1 PROCESSOR, SYSTEM, AND METHOD FOR EFFICIENT, HIGH-THROUGHPUT PROCESSING OF TWO-DIMENSIONAL, INTERRELATED DATA SETS 审中-公开
标题翻译：处理器，系统和方法，用于两维，中间数据集的高效率高通量处理
公开(公告)号：WO2014039210A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/054340
申请日：2013-08-09
申请人： MIREPLICA TECHNOLOGY, LLC , JOHNSON, William, M.
发明人： JOHNSON, William, M.
IPC分类号： G06F15/76 , G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F9/30043 , G06F9/3814 , G06F9/3824 , G06F9/3887 , G06F9/3893 , G06F15/80 , G06T1/60
摘要： Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage. This approach enables programmable visual computing with throughput approaching that of hardwired solutions.
摘要翻译：公开了系统，处理器和方法，用于组织处理数据通路以在执行单个程序时并行执行操作。每个数据路径使用新颖的指令排序方法执行相同的指令序列。每个数据路径通过具有划分成相同区域的数据存储器的处理器来实现。主处理器获取指令并将其传送到数据路径处理器。所有处理器都通过指令流水线连续连接，使得指令在并行数据路径中执行，每个数据通路在相邻数据路径中的执行时间偏移一个时钟周期。该系统包括互连网络，使得能够在水平和垂直维度上完全共享数据，具有将任何数据路径耦合到任何其他数据路径的存储器的效果，而不增加常用的处理循环。这种方法使可编程视觉计算的吞吐量接近硬连线解决方案。

2. 发明申请

WO2007092747A2 MULTI-CORE ARCHITECTURE WITH HARDWARE MESSAGING 审中-公开
标题翻译：具有硬件消声功能的多核心架构
公开(公告)号：WO2007092747A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/061509
申请日：2007-02-02
申请人： TEXAS INSTRUMENTS INCORPORATED , JOHNSON, William, M. , NYE, Jeffrey, L.
发明人： JOHNSON, William, M. , NYE, Jeffrey, L.
CPC分类号： G06F9/3851 , G06F9/3828 , G06F9/3891 , G06F15/167
摘要： Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits (200) include processors having dedicated messaging hardware (210) that enable processor cores (212) to minimize interrupt activity related to inter- core communications. The messaging hardware receives (604) and parses (610) any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.
摘要翻译：这里公开了一种用于设计数字电路的系统和方法。在一些实施例中，数字电路（200）包括具有使得处理器核心（212）能够最小化与核心间通信有关的中断活动的专用消息收发硬件（210）的处理器。在将消息的内容传递到数字电路之前，消息收发硬件接收（604）并解析（610）整个消息。在其他实施例中，数字电路功能在各个核之间进行分区以实现并行执行。每个核心可以被提供有标准化的消息传递硬件，其将所有其他内核的内部实现细节屏蔽。这种模块化方法加速了开发和测试，并且使并行电路设计更有效地实现了可行的加速。这些数字电路核可以是均匀的或异质的。

3. 发明申请

WO02058992A3 MINIATURE ATTITUDE SENSING SUITE 审中-公开
标题翻译： MINIATURE ATTITUDE感应套装
公开(公告)号：WO02058992A3
公开(公告)日：2003-02-27
申请号：PCT/US0202333
申请日：2002-01-28
申请人： DRAPER LAB CHARLES S , JOHNSON WILLIAM M , MUSOFF HOWARD , SARGENT DARRYL G , GILMORE JEROLD P , DENNEHY CORNELIUS J
发明人： JOHNSON WILLIAM M , MUSOFF HOWARD , SARGENT DARRYL G , GILMORE JEROLD P , DENNEHY CORNELIUS J
IPC分类号： B64G1/28 , B64G1/36 , B64G1/38 , G01C21/24 , G01C21/02 , G01S3/786 , G05D1/08
CPC分类号： B64G1/361 , B64G1/281 , B64G1/288 , B64G1/36 , B64G1/38
摘要： The present invention provides methods of and apparatus for determining the inertial attitude of an aerospace vehicle. In one embodiment, the invention provides a rotational astronomical object-sighting concept to determine the inertial attitude of an axis of the aerospace vehicle without the star identification or drawback. In another embodiment, the invention provides an attitude measurement apparatus comprising a high sensitivity optical sensor and a low power inertial sensor.
摘要翻译：本发明提供用于确定航空航天器的惯性姿态的方法和装置。在一个实施例中，本发明提供了旋转天文观测概念来确定航空航天车辆的轴的惯性姿态，而没有星号识别或缺点。在另一个实施例中，本发明提供一种包括高灵敏度光学传感器和低功率惯性传感器的姿态测量装置。

4. 发明申请

WO2002058992A2 MINIATURE ATTITUDE SENSING SUITE 审中-公开
标题翻译： MINIATURE ATTITUDE感应套装
公开(公告)号：WO2002058992A2
公开(公告)日：2002-08-01
申请号：PCT/US2002/002333
申请日：2002-01-28
申请人： THE CHARLES STARK DRAPER LABORATORY, INC. , JOHNSON, William, M. , MUSOFF, Howard , SARGENT, Darryl, G. , GILMORE, Jerold, P. , DENNEHY, Cornelius, J.
发明人： JOHNSON, William, M. , MUSOFF, Howard , SARGENT, Darryl, G. , GILMORE, Jerold, P. , DENNEHY, Cornelius, J.
IPC分类号： B64G
CPC分类号： B64G1/361 , B64G1/281 , B64G1/288 , B64G1/36 , B64G1/38
摘要： The present invention provides methods of and apparatus for determining the inertial attitude of an aerospace vehicle. In one embodiment, the invention provides a rotational astronomical object-sighting concept to determine the inertial attitude of an axis of the aerospace vehicle without the star identification or drawback. In another embodiment, the invention provides an attitude measurement apparatus comprising a high sensitivity optical sensor and a low power inertial sensor.
摘要翻译：本发明提供用于确定航空航天器的惯性姿态的方法和装置。在一个实施例中，本发明提供了旋转天文观测概念来确定航空航天车辆的轴的惯性姿态，而没有星号识别或缺点。在另一个实施例中，本发明提供一种包括高灵敏度光学传感器和低功率惯性传感器的姿态测量装置。

5. 发明申请

WO2007092747A3 MULTI-CORE ARCHITECTURE WITH HARDWARE MESSAGING 审中-公开
标题翻译：具有硬件消声功能的多核心架构
公开(公告)号：WO2007092747A3
公开(公告)日：2008-04-03
申请号：PCT/US2007061509
申请日：2007-02-02
申请人： TEXAS INSTRUMENTS INC , JOHNSON WILLIAM M , NYE JEFFREY L
发明人： JOHNSON WILLIAM M , NYE JEFFREY L
IPC分类号： G06F11/00
CPC分类号： G06F9/3851 , G06F9/3828 , G06F9/3891 , G06F15/167
摘要： Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits (200) include processors having dedicated messaging hardware (210) that enable processor cores (212) to minimize interrupt activity related to inter- core communications. The messaging hardware receives (604) and parses (610) any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.
摘要翻译：这里公开了一种用于设计数字电路的系统和方法。在一些实施例中，数字电路（200）包括具有使得处理器核心（212）能够最小化与核心间通信相关的中断活动的专用消息收发硬件（210）的处理器。在将消息的内容传递到数字电路之前，消息收发硬件接收（604）并解析（610）整个消息。在其他实施例中，数字电路功能在各个核之间进行分区以实现并行执行。每个核心可以被提供有标准化的消息传递硬件，其将所有其他内核的内部实现细节屏蔽。这种模块化方法加速了开发和测试，并且使并行电路设计更有效地实现了可行的加速。这些数字电路核可以是均匀的或异质的。

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