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1. 发明申请

WO2011119373A3 INTEGRATED CIRCUIT GUARD RINGS 审中-公开
标题翻译：集成电路保护环
公开(公告)号：WO2011119373A3
公开(公告)日：2011-12-22
申请号：PCT/US2011028522
申请日：2011-03-15
申请人： ALTERA CORP , JENSEN BRADLEY , CHU CHARLES Y
发明人： JENSEN BRADLEY , CHU CHARLES Y
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76229 , H01L21/31053
摘要： Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.
摘要翻译：提供带保护环的集成电路。集成电路可能包括对外部噪声源敏感的内部电路。保护环可环绕功能电路以将电路与噪声源隔离。保护环可以包括第一，第二和第三区域。第一和第三区域可以包括p阱。第二区域可以包括n阱。可以在三个区域中的衬底表面处形成扩散区域的条纹。未被扩散区占据的保护环中的区域被浅沟槽隔离（STI）结构占据。虚设结构的条纹可以形成在相应的STI结构上并且可以不与扩散区域重叠。第一和第三区域中的扩散区域可以被偏置到地电压。第二部分中的扩散区可以被偏置到正电源电压。

2. 发明申请

WO9715001A3 RISC MICROPROCESSOR ARCHITECTURE 审中-公开
标题翻译： RISC微处理器架构
公开(公告)号：WO9715001A3
公开(公告)日：1998-04-09
申请号：PCT/US9616013
申请日：1996-10-04
申请人： PATRIOT SCIENT CORP , SHAW GEORGE W , MCCLURG MARTIN G , JENSEN BRADLEY D , FISH RUSSEL H III , MOORE CHARLES H
发明人： SHAW GEORGE W , MCCLURG MARTIN G , JENSEN BRADLEY D , FISH RUSSEL H III , MOORE CHARLES H
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38 , G06F12/08 , G09G5/36 , G09G5/39 , G09G5/393 , G06F
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： MPU (108) contains 52 general-purpose registers, including 16 global data registers (104), an index register (132), a count register (134), a 16-deep addressable register/return stack (124), and an 18-deep operand stack (122). Both stacks contain an index register (128, or 130) in the top elements, are cached on chip, and, when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register (136) and 41 locally addressed registers (102) for I/O, control, configuration, and status. The CPU (100) contains both a high-performance, zero-operand, dual-stack architecture microprocessing unit (MPU) (108), and an input-output processor (IOP) (110) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions.

3. 发明申请

WO2010042542A2 METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS 审中-公开
标题翻译：金属氧化物金属电容器与酒吧VIAS
公开(公告)号：WO2010042542A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059729
申请日：2009-10-06
申请人： ALTERA CORPORATION , SARDANA, Charu , RATNAKUMAR, Albert , JENSEN, Bradley , WATT, Jeffrey, T.
发明人： SARDANA, Charu , RATNAKUMAR, Albert , JENSEN, Bradley , WATT, Jeffrey, T.
IPC分类号： H01L27/108 , H01L27/04
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.
摘要翻译：为集成电路提供带通孔的金属氧化物金属电容器。电容器可以形成在集成电路的互连层中。互连层中的堆叠的条形通孔和金属线可以连接以形成跨越多个互连层的导电垂直板。具有条形通孔的电容器可以通过将由堆叠的条形通孔和金属线形成的多个垂直板彼此平行地形成，交替相邻垂直平行板的极性而形成多个平行板电容器。平行板可以互连以在电容器中形成第一和第二端子。

4. 发明申请

WO1997015001A2 RISC MICROPROCESSOR ARCHITECTURE 审中-公开
标题翻译： RISC微处理器架构
公开(公告)号：WO1997015001A2
公开(公告)日：1997-04-24
申请号：PCT/US1996016013
申请日：1996-10-04
申请人： PATRIOT SCIENTIFIC CORPORATION , SHAW, George, W. , McCLURG, Martin, G. , JENSEN, Bradley, D. , FISH, Russel, H., III , MOORE, Charles, H.
发明人： PATRIOT SCIENTIFIC CORPORATION
IPC分类号： G06F00/00
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： The microprocessor (100) executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. The CPU instruction sets are hardwired, allowing most instructions to execute in a single cycle. A "flow-through" design allows the next instruction to start before the prior instruction completes, thus increasing performance. MPU (108) contains 52 general-purpose registers, including 16 global data registers (104), an index register (132), a count register (134), a 16-deep addressable register/return stack (124), and an 18-deep operand stack (122). Both stacks contain an index register (128, or 130) in the top elements, are cached on chip, and, when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register (136) and 41 locally addressed registers (102) for I/O, control, configuration, and status. The CPU (100) contains both a high-performance, zero-operand, dual-stack architecture microprocessing unit (MPU) (108), and an input-output processor (IOP) (110) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand (stack) architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU (108) and IOP (110) to issue and complete instructions in a single clock cycle - each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU (100) obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
摘要翻译：微处理器（100）以100MHz内部时钟频率执行100个本机MIPS峰值性能。 CPU指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 MPU（108）包含52个通用寄存器，包括16个全局数据寄存器（104），一个索引寄存器（132），一个计数寄存器（134），一个16深可寻址寄存器/返回堆栈（124）和一个18 - 操作数堆栈（122）。这两个堆栈都包含顶部元素中的索引寄存器（128或130），缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。此外，MPU包含用于I / O，控制，配置和状态的模式/状态寄存器（136）和41个本地寻址寄存器（102）。 CPU（100）包含执行指令以传送数据的计数事件的高性能零操作数双栈结构微处理单元（MPU）108和输入输出处理器（IOP）110，，测量时间，并执行其他与时序相关的功能。零操作数（堆栈）架构消除了操作数位。堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。指令简单易于解码和执行，允许MPU（108）和IOP（110）以单个时钟周期发出和完成指令 - 每个时钟周期为100个本地MIPS峰值执行。每当执行指令提取或预取时，CPU（100）使用8位操作码，最多可从存储器中获取四条指令。这些指令可以重复，而不会从内存重新读取。当直接连接到DRAM而没有高速缓存时，这将保持高性能。

5. 发明申请

WO2017136568A1 ATMOSPHERIC BALLOON WITH BALLONET WALL AND METHODS FOR SAME 审中-公开
标题翻译：带气囊壁的大气球和相同的方法
公开(公告)号：WO2017136568A1
公开(公告)日：2017-08-10
申请号：PCT/US2017/016239
申请日：2017-02-02
申请人： RAVEN INDUSTRIES, INC. , WICKERSHAM, Scott William , ZIMMERMAN, Michael William , JENSEN, Bradley Roger , WEGNER, Emily
发明人： WICKERSHAM, Scott William , ZIMMERMAN, Michael William , JENSEN, Bradley Roger , WEGNER, Emily
IPC分类号： B64B1/38 , B64B1/40 , B64B1/42 , B64B1/44 , B64B1/46 , B64B1/48 , B64B1/50 , B64B1/52 , B64B1/54 , B64B1/56
CPC分类号： B64B1/60
摘要： An atmospheric balloon assembly includes a balloon shell extending between upper and lower apexes. The balloon shell includes a plurality of shell gores, each of the shell gores includes first and second shell edges extending between the upper and lower apexes. A ballonet is coupled along the balloon shell, the ballonet includes a ballonet panel including first and second ballonet apexes and first and second ballonet edges extending between the first and second ballonet apexes. The first ballonet edge is coupled along one or more shell gores of the plurality of shell gores, and the second ballonet edge is coupled along another one or more shell gores of the plurality of shell gores.
摘要翻译：大气球囊组件包括在上下顶点之间延伸的球囊壳体。气球壳包括多个壳孔，每个壳孔包括在上下顶点之间延伸的第一和第二壳边缘。气囊沿着气囊壳体联接，气囊包括气囊板，该气囊板包括第一和第二气囊顶点以及在第一和第二气囊顶点之间延伸的第一和第二气囊边缘。第一气球边缘沿多个外壳砂砾的一个或多个外壳砂砾联接，并且第二气球外缘沿着多个外壳砂砾中的另一个或多个外壳砂砾联接。

6. 发明申请

WO2012018398A1 N-WELL/P-WELL STRAP STRUCTURES 审中-公开
标题翻译： N-WELL / P-WELL STRAP STRUCTURES
公开(公告)号：WO2012018398A1
公开(公告)日：2012-02-09
申请号：PCT/US2011/001378
申请日：2011-08-04
申请人： ALTERA CORPORATION , WHITE, Thomas, H. , POWELL, Giles, V. , JENSEN, Bradley , LAU, Swee, Aun , DO, Dustin , LEE, Andy, L. , LIN, Wuu-cherng
发明人： WHITE, Thomas, H. , POWELL, Giles, V. , JENSEN, Bradley , LAU, Swee, Aun , DO, Dustin , LEE, Andy, L. , LIN, Wuu-cherng
IPC分类号： H01L21/00
CPC分类号： H01L21/823493 , H01L21/32055 , H01L21/76224 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带来实现的较低要求。

7. 发明申请

WO2010042542A3 METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS 审中-公开
标题翻译： METAL-OXIDE-METAL电容器与酒吧VIAS
公开(公告)号：WO2010042542A3
公开(公告)日：2010-07-15
申请号：PCT/US2009059729
申请日：2009-10-06
申请人： ALTERA CORP , SARDANA CHARU , RATNAKUMAR ALBERT , JENSEN BRADLEY , WATT JEFFREY T
发明人： SARDANA CHARU , RATNAKUMAR ALBERT , JENSEN BRADLEY , WATT JEFFREY T
IPC分类号： H01L27/108 , H01L27/04
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.
摘要翻译：为集成电路提供带条形过孔的金属氧化物金属电容器。电容器可以形成在集成电路的互连层中。互连层中的堆叠条形过孔和金属线可以连接以形成跨越多个互连层的导电垂直板。具有条形过孔的电容器可以通过放置由堆叠条形过孔和金属线形成的多个垂直板彼此平行，交替相邻垂直平行板的极性以形成多个平行板电容器来形成。平行板可以互连以形成电容器中的第一和第二端子。

8. 发明申请

WO2011119373A2 INTEGRATED CIRCUIT GUARD RINGS 审中-公开
标题翻译：集成电路保护环
公开(公告)号：WO2011119373A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/028522
申请日：2011-03-15
申请人： ALTERA CORPORATION , JENSEN, Bradley , CHU, Charles, Y.
发明人： JENSEN, Bradley , CHU, Charles, Y.
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76229 , H01L21/31053
摘要： Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.
摘要翻译：提供带保护环的集成电路。集成电路可以包括对外部噪声源敏感的内部电路。保护环可以围绕功能电路以将电路与噪声源隔离。保护环可以包括第一，第二和第三区域。第一和第三区域可以包括p阱。第二区域可以包括n阱。扩散区域的条纹可以形成在三个区域中的基板的表面。保护环中未被扩散区占据的区域被浅沟槽隔离（STI）结构所占据。虚设结构的条纹可以形成在相应的STI结构上，并且可能不与扩散区重叠。第一和第三区域中的扩散区域可被偏压到接地电压。第二部分中的扩散区域可以被偏置到正电源电压。

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