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2. 发明申请

WO1997015001A2 RISC MICROPROCESSOR ARCHITECTURE 审中-公开
标题翻译： RISC微处理器架构
公开(公告)号：WO1997015001A2
公开(公告)日：1997-04-24
申请号：PCT/US1996016013
申请日：1996-10-04
申请人： PATRIOT SCIENTIFIC CORPORATION , SHAW, George, W. , McCLURG, Martin, G. , JENSEN, Bradley, D. , FISH, Russel, H., III , MOORE, Charles, H.
发明人： PATRIOT SCIENTIFIC CORPORATION
IPC分类号： G06F00/00
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： The microprocessor (100) executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. The CPU instruction sets are hardwired, allowing most instructions to execute in a single cycle. A "flow-through" design allows the next instruction to start before the prior instruction completes, thus increasing performance. MPU (108) contains 52 general-purpose registers, including 16 global data registers (104), an index register (132), a count register (134), a 16-deep addressable register/return stack (124), and an 18-deep operand stack (122). Both stacks contain an index register (128, or 130) in the top elements, are cached on chip, and, when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register (136) and 41 locally addressed registers (102) for I/O, control, configuration, and status. The CPU (100) contains both a high-performance, zero-operand, dual-stack architecture microprocessing unit (MPU) (108), and an input-output processor (IOP) (110) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand (stack) architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU (108) and IOP (110) to issue and complete instructions in a single clock cycle - each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU (100) obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
摘要翻译：微处理器（100）以100MHz内部时钟频率执行100个本机MIPS峰值性能。 CPU指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 MPU（108）包含52个通用寄存器，包括16个全局数据寄存器（104），一个索引寄存器（132），一个计数寄存器（134），一个16深可寻址寄存器/返回堆栈（124）和一个18 - 操作数堆栈（122）。这两个堆栈都包含顶部元素中的索引寄存器（128或130），缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。此外，MPU包含用于I / O，控制，配置和状态的模式/状态寄存器（136）和41个本地寻址寄存器（102）。 CPU（100）包含执行指令以传送数据的计数事件的高性能零操作数双栈结构微处理单元（MPU）108和输入输出处理器（IOP）110，，测量时间，并执行其他与时序相关的功能。零操作数（堆栈）架构消除了操作数位。堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。指令简单易于解码和执行，允许MPU（108）和IOP（110）以单个时钟周期发出和完成指令 - 每个时钟周期为100个本地MIPS峰值执行。每当执行指令提取或预取时，CPU（100）使用8位操作码，最多可从存储器中获取四条指令。这些指令可以重复，而不会从内存重新读取。当直接连接到DRAM而没有高速缓存时，这将保持高性能。

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