专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO0189092A9 APPARATUS FOR RADIO FREQUENCY PROCESSING WITH DUAL MODULUS SYNTHESIZER 审中-公开
标题翻译：用于双模态合成器的无线电频率处理的装置
公开(公告)号：WO0189092A9
公开(公告)日：2004-03-04
申请号：PCT/US0114536
申请日：2001-05-07
申请人： INTERSIL CORP
发明人： BLACK ERIC , ROBERTS RICHARD
IPC分类号： H03L7/183 , H03D7/16 , H04L7/00 , H04L27/12 , H04L27/152
CPC分类号： H03D7/163 , H03D7/165
摘要： An appparatus for radio frequency processing includes a local oscillator synthesizer circuit having a voltage controlled oscillator that generates an oscillator signal f1. A divide-by-N circuit receives the oscillator circuit f1 and divdes that signal to produce an f1/N oscillator signal. A dual modulus synthesizer is connected to the divide-by-N circuit and generates a quadrature modulus signal f1/N. A receiver circuit and a transmitter circuit are operatively connected to the local oscillator synthesizer circuit. Each of the receiver circuits and transmitter circuits has at least two mixer circuits for mixing and respectively down converting/up converting intermediate radio frequency singals.
摘要翻译：用于射频处理的设备包括具有产生振荡器信号f1的压控振荡器的本地振荡器合成器电路。 N分频电路接收振荡器电路f1并将该信号除去以产生f1 / N振荡器信号。双模合成器连接到N分频电路并产生正交模数信号f1 / N。接收机电路和发射机电路可操作地连接到本地振荡器合成器电路。每个接收机电路和发射机电路具有至少两个混频器电路，用于混合和分别下变频/上变换中间射频信号。

2. 发明申请

WO0209277A3 NEGATIVE FEEDBACK GAIN CONTROL FOR COMMON ELECTRODE TRANSISTOR 审中-公开
标题翻译：用于常用电极晶体管的负反馈增益控制
公开(公告)号：WO0209277A3
公开(公告)日：2003-01-23
申请号：PCT/US0121722
申请日：2001-07-10
申请人： INTERSIL CORP
发明人： FURINO JAMES
IPC分类号： H03G3/12 , H03F1/34 , H03G1/00
CPC分类号： H03G1/0052 , H03F1/34 , H03F2200/151 , H03G1/0082
摘要： The unwanted varation in operating point asscoiated with varying gain of a common input/output electrode transistor, such as a common emitter bipolar transistor, is obviated by coupling an electronically controllable conductance in a negative feedback path between a first input/output electrode (collector) and the control electrode (base) of the transistor. A first embodiment applied to a bipolar device, the electronically controlled feedback element comprises a diode, having its forward conductance varied by adjusting current flow through a controllable current source. The controls the amount of feedback from the collector to the base and the forward loop gain of the common emitter transistor. A second embodiment for a bipolar device, the controlled feedback element comprises an emitter-follower transistor, with its forward gain controlled by varying the current drawn through its emitter by a controllable current source/sink. This, in turn, varies the amount of voltage fed back from the collector to the base and thus the gain of the common emitter trasistor.
摘要翻译：通过在第一输入/输出电极（集电极）之间的负反馈路径中耦合电子可控制的电导，消除了与公共输入/输出电极晶体管（例如公共射极双极晶体管）的增益变化相对应的工作点中的不需要的变化，和晶体管的控制电极（基极）。应用于双极器件的第一实施例中，电子控制的反馈元件包括二极管，其正向电导通过调节通过可控电流源的电流而变化。控制从集电极到基极的反馈量以及共发射极晶体管的正向环路增益。用于双极器件的第二实施例中，受控反馈元件包括射极跟随器晶体管，其前向增益通过改变通过可控电流源/吸收器通过其发射极吸取的电流而被控制。这反过来又改变了从集电极反馈到基极的电压量，从而改变了公共发射极导管的增益。

3. 发明申请

WO0173532A3 METHODS TO CONTROL THE DROOP WHEN POWERING DUAL MODE PROCESSORS AND ASSOCIATED CIRCUITS 审中-公开
标题翻译：控制双模式处理器和相关电路供电时的方法
公开(公告)号：WO0173532A3
公开(公告)日：2002-08-22
申请号：PCT/US0109315
申请日：2001-03-23
申请人： INTERSIL CORP
发明人： MURATOV VOLODYMYR , COLETTA MICHAEL , WIKTOR WLODZIMERZ
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , Y02D10/126
摘要： A DC/DC converter (100) has a DAC (40) that receives a code associated with desired processor operating voltage and sets the reference voltage on its output (41). The reference voltage (VDAC) is boosted by the buffer amplifier (42) to center the droop along the median load. A sensed current signal ICS (22) is proportional to the load current IO (24) and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain GC. A droop control feedback circuit includes an error amplifier (50). It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPUmax and transformed to the current IDROOP (32) amplifier output. As a result, the output voltage of the converter (50) is inversely proportional to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover.
摘要翻译： DC / DC转换器（100）具有DAC（40），其接收与期望的处理器工作电压相关联的代码并在其输出端（41）上设置参考电压。参考电压（VDAC）由缓冲放大器（42）升压，以使下降沿中间负载中心。感测的电流信号ICS（22）与负载电流IO（24）成比例，可以是电感电流或开关电流或二极管（或同步开关）电流。在所有情况下，按照增益GC的因子进行缩小。下降控制反馈电路包括误差放大器（50）。它有两个输入。在一个实施例中，转换器的增益是与处理器时钟频率FCPUmax成反比的信号，并转换成当前的IDROOP（32）放大器输出。结果，转换器（50）的输出电压与负载电流成反比，并且与处理器模式切换相关联的处理器时钟频率变化是不变的。

4. 发明申请

WO0189082A3 AN ULTRA LINEAR HIGH FREQUENCY TRANSCONDUCTOR STRUCTURE 审中-公开
标题翻译：超线性高频交叉结构
公开(公告)号：WO0189082A3
公开(公告)日：2002-05-30
申请号：PCT/US0140680
申请日：2001-05-07
申请人： INTERSIL CORP
发明人： MYERS BRENT , GANTI RAMKISHORE
IPC分类号： H03F3/45 , H03F1/32 , H03F3/26
CPC分类号： H03F3/45937 , H03F3/45511 , H03F2203/45356 , H03F2203/45394 , H03F2203/45404 , H03F2203/45418
摘要： A transductor block including a Czarnul tuning network, transconductance resistors, an input voltage follower amplifier, a common mode circuit, PMOS transistors couples in cascode configuration, an input current source, and high gain amplifiers that drive NMOS transistors at the output. The input voltage follower amplifier receives a differential input signal including a common mode voltage and applies the differential input signal to the Czarnul tuning network. The Czarnul tuning network includes series resistors and is coupled in parallel with the transconductance resistors. The common mode circuit receives the differential input signal and a reference common mode voltage and provides a bias voltage and a common mode output PMOS transistors to establish a DC output current and to minimize drift of the comon mode voltage of the transconductance block. Also, the bias voltage is level shifted from the common mode signal. The high gain amplifiers maintain the output of the Czarnul tuning network and transconductance resistors at the bias voltage.
摘要翻译：包括Czarnul调谐网络，跨导电阻器，输入电压跟随放大器，共模电路，PMOS共栅组合的PMOS晶体管，输入电流源和在输出端驱动NMOS晶体管的高增益放大器的转换器块。输入电压跟随器放大器接收包括共模电压的差分输入信号，并将差分输入信号施加到Czarnul调谐网络。 Czarnul调谐网络包括串联电阻，并与跨导电阻并联耦合。共模电路接收差分输入信号和参考共模电压，并提供偏置电压和共模输出PMOS晶体管以建立DC输出电流并最小化跨导块的共模模式电压的漂移。此外，偏置电压从共模信号电平移位。高增益放大器保持Czarnul调谐网络和跨导电阻在偏置电压下的输出。

5. 发明申请

WO0205442A3 ESTIMATION OF WIRELESS CHANNEL IMPULSE RESPONSE USING A PREAMBLE 审中-公开
标题翻译：使用前瞻性估计无线通道冲突响应
公开(公告)号：WO0205442A3
公开(公告)日：2002-05-16
申请号：PCT/US0121648
申请日：2001-07-10
申请人： INTERSIL CORP
发明人： WEBSTER MARK , BALDWIN KEITH , NELSON GEORGE
IPC分类号： H04B7/005 , H04B3/06 , H04L25/02
CPC分类号： H04L25/0236 , H04L25/0212
摘要： A channel estimator for use with the wireless digital data receiver facilitates processing of a preamble symbol sequence received over a multipath communication channel to enable the impulse response of the channel to be rapidly estimated, and set the parameters of the receiver's decision feedback equalizer. During the preamble dwell interval, selected estimates of one or more received preamble symbols within a plurality of successive data symbols are repeated, in order to generate a longer sequence of preamble symbol estimates. The receiver's processor then employs this longer sequence of data symbol values, to solve an associated set of linear equations for estimating the multipath channel's impulse response.
摘要翻译：与无线数字数据接收器一起使用的信道估计器有助于处理通过多路径通信信道接收的前导符号序列，以使得能够快速估计信道的脉冲响应，并设置接收机的判决反馈均衡器的参数。在前导码驻留间隔期间，重复多个连续数据符号内的一个或多个接收到的前导码符号的所选估计，以便产生更长序列的前导码符号估计。接收机的处理器然后采用这种更长的数据符号值序列，以求解用于估计多路径信道的脉冲响应的相关联的线性方程组。

6. 发明申请

WO0184697A3 DC TO DC CONVERTER METHOD AND CIRCUITRY 审中-公开
标题翻译：直流到直流转换器的方法和电路
公开(公告)号：WO0184697A3
公开(公告)日：2002-03-07
申请号：PCT/US0114168
申请日：2001-05-02
申请人： INTERSIL CORP , MURATOV VOLODYMYR , HODGINS ROBERT , JOCHUM THOMAS
发明人： MURATOV VOLODYMYR , HODGINS ROBERT , JOCHUM THOMAS
IPC分类号： H02M3/156 , H02M3/158
CPC分类号： H02M3/1563 , H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： A DC-to-DC converter has a pulse width modulator (PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.
摘要翻译： DC-DC转换器具有脉宽调制器（PWM）和迟滞（波动）调制器。对于低电流负载，选择迟滞调制器; 对于高电流负载，选择PWM。模式选择开关在每个开关周期结束时感测开关输出电压的极性。如果极性从一个周期变化到下一个周期，则该模式可以立即改变到另一个模式。计数器用于在每个周期结束时记录极性，并且可以通过计数器延迟从一个模式切换到另一个模式，以防止基于杂散输出电压波动的变化模式。

7. 发明申请

WO0215382A3 OSCILLATOR HAVING REDUCED SENSITIVITY TO SUPPLY VOLTAGE CHANGES 审中-公开
标题翻译：具有降低灵敏度以提供电压变化的振荡器
公开(公告)号：WO0215382A3
公开(公告)日：2003-02-13
申请号：PCT/US0125578
申请日：2001-08-11
申请人： INTERSIL CORP
发明人： SHEARON WILLIAM , VULIH SALOMON
IPC分类号： H03K3/0231 , H03K4/502 , H03K3/354 , H03K3/011
CPC分类号： H03K4/502 , H03K3/0231
摘要： An oscillator includes a first sawtooth waveform generator for generating a first sawtooth waveform having a selectively started ramp portion and a second sawtooth waveform generator for generating a second sawtooth waveform having a selectively started ramp portion. A controller is also included for alternatingly controlling the first and second sawtooth waveform generators so that a transition to the ramp portion of one sawtooth waveform is based upon determining the ramp portion of the other sawtooth waveform reaching a trip point. The controller also sets the trip point substantially independent of a supply voltage.
摘要翻译：振荡器包括：第一锯齿波形发生器，用于产生具有选择性起动斜坡部分的第一锯齿波形;以及第二锯齿波形发生器，用于产生具有选择性启动斜坡部分的第二锯齿波形。还包括用于交替地控制第一和第二锯齿波形发生器的控制器，使得到达一个锯齿形波形的斜坡部分的转变是基于确定另一锯齿波形的斜坡部分达到跳变点。控制器还设置跳闸点基本上与电源电压无关。

8. 发明申请

WO0189092A2 APPARATUS FOR RADIO FREQUENCY PROCESSING WITH DUAL MODULUS SYNTHESIZER 审中-公开
标题翻译：用于双模态合成器的无线电频率处理的装置
公开(公告)号：WO0189092A2
公开(公告)日：2001-11-22
申请号：PCT/US0114536
申请日：2001-05-07
申请人： INTERSIL CORP
发明人： BLACK ERIC , ROBERTS RICHARD
IPC分类号： H03L7/183 , H03D7/16 , H04L7/00 , H04L27/12 , H04L27/152 , H03L
CPC分类号： H03D7/163 , H03D7/165
摘要： An appparatus for radio frequency processing includes a local oscillator synthesizer circuit having a voltage controlled oscillator that generates an oscillator signal f1. A divide-by-N circuit receives the oscillator circuit f1 and divdes that signal to produce an f1/N oscillator signal. A dual modulus synthesizer is connected to the divide-by-N circuit and generates a quadrature modulus signal f1/N. A receiver circuit and a transmitter circuit are operatively connected to the local oscillator synthesizer circuit. Each of the receiver circuits and transmitter circuits has at least two mixer circuits for mixing and respectively down converting/up converting intermediate radio frequency singals.
摘要翻译：用于射频处理的设备包括具有产生振荡器信号f1的压控振荡器的本地振荡器合成器电路。 N分频电路接收振荡器电路f1并将该信号除去以产生f1 / N振荡器信号。双模合成器连接到N分频电路并产生正交模数信号f1 / N。接收机电路和发射机电路可操作地连接到本地振荡器合成器电路。每个接收机电路和发射机电路具有至少两个混频器电路，用于混合和分别下变频/上变换中间射频信号。

9. 发明申请

WO0159848A3 MOS-GATED SEMICONDUCTOR DEVICE HAVING ALTERNATING CONDUCTIVITY TYPE SEMICONDUCTOR REGIONS AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：具有交替电导型半导体区域的MOS栅极半导体器件及其制造方法
公开(公告)号：WO0159848A3
公开(公告)日：2002-05-02
申请号：PCT/US0102964
申请日：2001-01-30
申请人： INTERSIL CORP
发明人： KOCON CHRISTOPHER
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/1095 , H01L29/7813
摘要： A MOS-gated device (100) such as a power MOSFET comprising well region extensions (432, 434) extending from respective well regions (103) into a drift region (102) of the device to deplete charge from said drift region (102) when a blocking voltage is applied. The well region extensions (432, 434) are formed in the sidewalls of trenches (152, 153) filled with an insulator such as low temperature oxide.
摘要翻译： MOS选通装置（100），例如功率MOSFET，其包括从相应的阱区域（103）延伸到装置的漂移区域（102）的阱区延伸部（432,434），以从所述漂移区域（102）中消耗电荷，当施加阻挡电压时。阱区域延伸部（432,434）形成在填充有诸如低温氧化物的绝缘体的沟槽（152,153）的侧壁中。

10. 发明申请

WO03034501A2 INTEGRATED CIRCUIT WITH A MOS STRUCTURE HAVING REDUCED PARASITIC BIPOLAR TRANSISTOR ACTION 审中-公开
标题翻译：具有减少的PARASITIC BIPOLAR TRANSISTOR动作的MOS结构的集成电路
公开(公告)号：WO03034501A2
公开(公告)日：2003-04-24
申请号：PCT/US0232121
申请日：2002-10-08
申请人： INTERSIL CORP
发明人： BEASOM JAMES D
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/04 , H01L27/092 , H01L29/165 , H01L29/739 , H01L29/78 , H01L31/12 , H01L21/336 , H01L21/762 , H01L21/84 , H03K17/082 , H03K17/691 , H03K17/785
CPC分类号： H01L29/7813 , H01L27/0921 , H01L29/1095 , H01L29/165 , H01L29/7801 , H01L29/7809 , H01L29/7835
摘要： An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.
摘要翻译：具有减小的寄生双极晶体管作用的MOS结构的集成电路。在一个实施例中，MOS集成电路器件包括具有工作表面的衬底，至少一个主体区域，并且每个体区域具有源区和窄带隙材料层。每个主体区域在靠近基板的工作表面的基板中形成。每个窄带隙材料层位于其相关联的主体区域的一部分中并且靠近基板的工作表面。每个窄带隙材料层具有窄于其中形成每个体区的衬底的带隙的带隙。每个源区形成在相关联的身体区域中。每个源区域的至少一部分也形成在窄带隙材料的相关层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式