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1. 发明申请

WO0184697A3 DC TO DC CONVERTER METHOD AND CIRCUITRY 审中-公开
标题翻译：直流到直流转换器的方法和电路
公开(公告)号：WO0184697A3
公开(公告)日：2002-03-07
申请号：PCT/US0114168
申请日：2001-05-02
申请人： INTERSIL CORP , MURATOV VOLODYMYR , HODGINS ROBERT , JOCHUM THOMAS
发明人： MURATOV VOLODYMYR , HODGINS ROBERT , JOCHUM THOMAS
IPC分类号： H02M3/156 , H02M3/158
CPC分类号： H02M3/1563 , H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： A DC-to-DC converter has a pulse width modulator (PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.
摘要翻译： DC-DC转换器具有脉宽调制器（PWM）和迟滞（波动）调制器。对于低电流负载，选择迟滞调制器; 对于高电流负载，选择PWM。模式选择开关在每个开关周期结束时感测开关输出电压的极性。如果极性从一个周期变化到下一个周期，则该模式可以立即改变到另一个模式。计数器用于在每个周期结束时记录极性，并且可以通过计数器延迟从一个模式切换到另一个模式，以防止基于杂散输出电压波动的变化模式。

2. 发明申请

WO0173532A3 METHODS TO CONTROL THE DROOP WHEN POWERING DUAL MODE PROCESSORS AND ASSOCIATED CIRCUITS 审中-公开
标题翻译：控制双模式处理器和相关电路供电时的方法
公开(公告)号：WO0173532A3
公开(公告)日：2002-08-22
申请号：PCT/US0109315
申请日：2001-03-23
申请人： INTERSIL CORP
发明人： MURATOV VOLODYMYR , COLETTA MICHAEL , WIKTOR WLODZIMERZ
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , Y02D10/126
摘要： A DC/DC converter (100) has a DAC (40) that receives a code associated with desired processor operating voltage and sets the reference voltage on its output (41). The reference voltage (VDAC) is boosted by the buffer amplifier (42) to center the droop along the median load. A sensed current signal ICS (22) is proportional to the load current IO (24) and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain GC. A droop control feedback circuit includes an error amplifier (50). It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPUmax and transformed to the current IDROOP (32) amplifier output. As a result, the output voltage of the converter (50) is inversely proportional to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover.
摘要翻译： DC / DC转换器（100）具有DAC（40），其接收与期望的处理器工作电压相关联的代码并在其输出端（41）上设置参考电压。参考电压（VDAC）由缓冲放大器（42）升压，以使下降沿中间负载中心。感测的电流信号ICS（22）与负载电流IO（24）成比例，可以是电感电流或开关电流或二极管（或同步开关）电流。在所有情况下，按照增益GC的因子进行缩小。下降控制反馈电路包括误差放大器（50）。它有两个输入。在一个实施例中，转换器的增益是与处理器时钟频率FCPUmax成反比的信号，并转换成当前的IDROOP（32）放大器输出。结果，转换器（50）的输出电压与负载电流成反比，并且与处理器模式切换相关联的处理器时钟频率变化是不变的。

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