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1. 发明申请

WO2008044778A1 METHOD FOR FABRICATING SEMICONDUCTOR CHIP 审中-公开
标题翻译：制造半导体芯片的方法
公开(公告)号：WO2008044778A1
公开(公告)日：2008-04-17
申请号：PCT/JP2007/070016
申请日：2007-10-05
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , ARITA, Kiyoshi , HAJI, Hiroshi
发明人： ARITA, Kiyoshi , HAJI, Hiroshi
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , B23K2203/42 , B23K2203/50 , H01L24/743 , H01L2224/743 , H01L2924/12042 , H01L2924/00
摘要： After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer 6, thereby making a surface 1c of a semiconductor wafer 1 exposed. The exposed surface 1c of the semiconductor wafer 1 in the boundary trenches 7 is etched by means of plasma of a fluorine-based gas, and the semiconductor wafer 1 is sliced into semiconductor chips 1' along the boundary trenches 7.
摘要翻译：在半导体晶片1上设置由芯片附着膜4和UV带5形成的膜层6作为掩模，形成在电路图案形成表面1a上形成的半导体元件2的边界沟槽7形成在膜层6，从而使半导体晶片1的表面1c露出。边界槽7中的半导体晶片1的露出面1c利用氟系气体的等离子体进行蚀刻，半导体晶片1沿着边界沟槽7切割成半导体芯片1'。

2. 发明申请

WO2008023849A1 METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP AND METHOD FOR PROCESSING SEMICONDUCTOR WAFER 审中-公开
标题翻译：制造半导体芯片的方法和加工半导体晶片的方法
公开(公告)号：WO2008023849A1
公开(公告)日：2008-02-28
申请号：PCT/JP2007/066960
申请日：2007-08-24
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , HAJI, Hiroshi , ARITA, Kiyoshi
发明人： HAJI, Hiroshi , ARITA, Kiyoshi
IPC分类号： H01L21/78 , H01L21/308
CPC分类号： H01L21/78 , B23K26/40 , B23K2203/50 , B28D5/00 , H01L21/0337 , H01L21/3086
摘要： In a laser processing step S3, boundary sections among semiconductor elements 2 of a resist film 4 are exposed to a laser beam 13a, to thus form in the resist film 4 boundary grooves 5-which partition the semiconductor elements 2 from each other-and to uncover a surface 1b of a semiconductor wafer 1 in the boundary grooves 5. In a plasma etching step S6, the surface 1b of the semiconductor wafer 1 exposed in the boundary grooves 5 is etched by means of plasma Pf of a fluorine-based gas, to thus separate the semiconductor wafer 1 into individual semiconductor chips 1' along the boundary grooves 5. Between the laser processing step S3 and the plasma etching step S6, there is performed processing pertaining to a boundary-groove-surface smoothing step S5 for smoothing, by means of plasma Po of oxygen gas, surfaces of the boundary grooves 5 having assumed an irregular shape in the laser processing step S3.
摘要翻译：在激光加工步骤S3中，抗蚀剂膜4的半导体元件2之间的边界部分暴露于激光束13a，从而在抗蚀剂膜4中形成边界槽5，边界槽5将半导体元件2彼此分隔开，并且形成为在边界槽5中露出半导体晶片1的表面1b。在等离子体蚀刻步骤S6中，通过氟基气体的等离子体Pf蚀刻在边界槽5中露出的半导体晶片1的表面1b，从而将半导体晶片1沿着边界槽5分离成单独的半导体芯片1'。在激光加工步骤S3和等离子体蚀刻步骤S6之间，进行与边界槽表面平滑化步骤S5相关的处理，通过氧化气体的等离子体Po，在激光加工步骤S3中边界槽5的表面具有不规则形状。

3. 发明申请

WO2006038699A1 METHOD FOR DIVIDING SEMICONDUCTOR WAFER AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件分割方法及半导体器件的制造方法
公开(公告)号：WO2006038699A1
公开(公告)日：2006-04-13
申请号：PCT/JP2005/018713
申请日：2005-10-04
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , HAJI, Hiroshi , ARITA, Kiyoshi , NAKAGAWA, Akira , NODA, Kazuhiro
发明人： HAJI, Hiroshi , ARITA, Kiyoshi , NAKAGAWA, Akira , NODA, Kazuhiro
IPC分类号： H01L21/78
CPC分类号： H01L21/78
摘要： In a semiconductor wafer including a plurality of imaginary-divided-regions which are partitioned by imaginary-dividing-lines that are respectively arranged in a grid-like arrangement on the semiconductor wafer and a circumferential line that is the outer periphery outline of the semiconductor wafer, a mask is placed so as to expose an entirety of surfaces of the wafer corresponding to respective removal-regions, the removal-regions being regions in approximately triangular form partitioned by the circumferential line of the wafer and the imaginary-dividing-lines and being some of the imaginary-divided-regions, and then plasma etching is performed on a mask placement-side surface, by which the semiconductor wafer is divided into the individual semiconductor devices along dividing lines while portions correspond to the removal-regions in the wafer are removed.
摘要翻译：在半导体晶片中，具有分别由在半导体晶片上排列成格子状排列的虚拟分割线分隔的多个虚分割区域和作为半导体晶片的外周轮廓的周向线放置掩模以暴露与各个去除区域对应的晶片的整个表面，去除区域是由晶片的圆周线和假想分界线分隔的约三角形形状的区域，并且为一些假想分割区域，然后在掩模放置侧表面上执行等离子体蚀刻，通过该掩模放置侧表面，半导体晶片沿着分割线被分割成各个半导体器件，而部分对应于晶片中的去除区域除去。

4. 发明申请

WO2006013910A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES, AND FORMATION APPARATUS FOR SEMICONDUCTOR WAFER DICING MASKS 审中-公开
标题翻译：半导体器件的制造方法和半导体波导贴片的形成装置
公开(公告)号：WO2006013910A1
公开(公告)日：2006-02-09
申请号：PCT/JP2005/014261
申请日：2005-07-28
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , HAJI, Hiroshi , ARITA, Kiyoshi , NISHINAKA, Teruaki
发明人： HAJI, Hiroshi , ARITA, Kiyoshi , NISHINAKA, Teruaki
IPC分类号： H01L21/78
CPC分类号： H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.
摘要翻译：在其中形成有多个半导体器件的半导体晶片的掩模放置侧表面上，设置掩模，同时定义用于将半导体晶片切割成各自的分离的半导体器件的切割线和有缺陷的半导体器件的表面在各个半导体器件中部分曝光，然后将等离子体蚀刻施加到半导体晶片的掩模放置侧表面，以便沿着限定的切割线将半导体晶片切割成各个半导体器件，并且将暴露部分去除有缺陷的半导体器件，以形成作为有缺陷的半导体器件区分标记的去除部分。

5. 发明申请

WO2005101943A2 ELECTRONIC COMPONENT MOUNTING APPARATUS AND METHOD OF MOUNTING ELECTRONIC COMPONENTS 审中-公开
标题翻译：电子元件安装装置和安装电子元件的方法
公开(公告)号：WO2005101943A2
公开(公告)日：2005-10-27
申请号：PCT/JP2005/007276
申请日：2005-04-08
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , HAJI, Hiroshi , OZONO, Mitsuru
发明人： HAJI, Hiroshi , OZONO, Mitsuru
IPC分类号： H05K13/00
CPC分类号： H01L21/67144 , H01L21/67132 , H01L21/681 , H01L21/6838 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/53039 , Y10T29/53174 , Y10T29/53178
摘要： In an electronic component mounting process for mounting electronic components (6) to a substrate (13), each of the electronic components (6) having an adhesive layer on a surface to be bonded to the substrate (13) is picked up with suction nozzle (33a) provided with individual heater (49), and a time taken for the mounting operation is so allotted that a first heating time (T1) of a duration from a moment when the suction nozzle (33a) comes into contact with the electronic component (6) for picking it up till another moment immediately before it begins a mounting motion to the substrate (13) is longer than a second heating time (T2) of a duration from the moment when the suction nozzle (33a) begins the mounting motion till another moment when it leaves the electronic component (6) mounted to the substrate (13).
摘要翻译：在将电子部件（6）安装到基板（13）的电子部件安装工序中，在与基板（13）接合的表面上具有粘接层的各电子部件（6）被吸引吸嘴（33a），设置有单独的加热器（49），并且分配用于安装操作的时间，使得从吸嘴（33a）与电子部件接触的时刻的持续时间的第一加热时间（T1）（6），用于将其拾取直到其开始向衬底（13）的安装运动之前的另一时刻长于从吸嘴（33a）开始安装运动的时刻开始的持续时间的第二加热时间（T2）直到其离开安装到基板（13）的电子部件（6）的另一时刻。

6. 发明申请

WO2004071149A1 ELECTRONIC COMPONENT MOUNTING APPARATUS AND ELECTRONIC COMPONENT MOUNTING METHOD 审中-公开
标题翻译：电子元件安装设备和电子元件安装方法
公开(公告)号：WO2004071149A1
公开(公告)日：2004-08-19
申请号：PCT/JP2004/001340
申请日：2004-02-09
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , HAJI, Hiroshi
发明人： HAJI, Hiroshi
IPC分类号： H05K13/04
CPC分类号： H01L24/81 , H01L24/75 , H05K13/08 , Y10T29/49131
摘要： In an electronic component mounting method in which electronic components are sucked/held by plural respective nozzles provided on a mounting head so as to be mounted on electronic component mounting portions of a board, such a mounting operation is sequentially carried out as to all of the electronic components, in which the electronic components, are sucked/held by the plural nozzles; an electronic component sucked/held by one of the plural nozzles is provisionally positioned above one electronic component mounting portion; both this electronic component and the electronic component mounting portion are observed by an observation head which is located between the board and the mounting head; a relative position detecting operation for detecting a relative positional relationship between this electronic component and the electronic component mounting portion is carried out as to all of the electronic components held by the mounting head; and the electronic component is positioned with respect to the electronic component mounting portion so as to be mounted thereon while the detected relative positional relationship is reflected
摘要翻译：在电子部件安装方法中，电子部件由设置在安装头上的多个喷嘴吸引/保持以安装在电路板的电子部件安装部上，这样的安装操作依次执行于所有其中电子部件被多个喷嘴吸住/保持的电子部件; 由多个喷嘴中的一个吸引/保持的电子部件临时定位在一个电子部件安装部上方; 通过位于板和安装头之间的观察头来观察该电子部件和电子部件安装部分; 对于由安装头保持的所有电子部件，执行用于检测该电子部件与电子部件安装部之间的相对位置关系的相对位置检测动作。并且电子部件相对于电子部件安装部被定位成安装在其上，同时反映检测到的相对位置关系

7. 发明申请

WO2008081968A1 MANUFACTURING METHOD OF SEMICONDUCTOR CHIP 审中-公开
标题翻译：半导体芯片的制造方法
公开(公告)号：WO2008081968A1
公开(公告)日：2008-07-10
申请号：PCT/JP2007/075368
申请日：2007-12-26
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , ARITA, Kiyoshi , HAJI, Hiroshi
发明人： ARITA, Kiyoshi , HAJI, Hiroshi
IPC分类号： H01L21/78 , H01L21/308 , H01L21/304
CPC分类号： H01L21/78 , H01L21/304 , H01L21/67092
摘要： An object is to provide a manufacturing method of a semiconductor chip, by which while a semiconductor wafer is not broken when the semiconductor wafer is transported before plasma dicing is carried out, a time required for the plasma dicing can be shortened, so that a manufacturing efficiency of the semiconductor chips can be improved. After a resist film 6 has been formed on a ground rear plane 1q of a semiconductor wafer 1, partial portions (6a and 1b) of cutting margin areas (6a, 1b, 1c, 3c) along dicing lines 2 are removed by a blade 13 corresponding to a mechanical cutting means, and thickness "t" of remaining cutting margin areas 1c of the semiconductor wafer 1 along a thickness direction thereof are made thinner, which never causes any problem when the semiconductor wafer 1 is transported. Thereafter, all of the remaining cutting margin areas (1c, 3a) are removed by performing a plasma etching process.
摘要翻译：本发明的目的是提供一种半导体芯片的制造方法，通过该半导体芯片的制造方法，在半导体晶片在进行等离子体切割之前被输送时半导体晶片不破裂的情况下，可以缩短等离子体切割所需的时间，从而制造可以提高半导体芯片的效率。在半导体晶片1的接地背面1q上形成抗蚀剂膜6之后，沿着切割线2切割边缘区域（6a，1b，1c，3c）的部分部分（6a和1b）被刀片13 对应于机械切割装置，并且半导体晶片1的厚度方向上的剩余切割边缘区域1c的厚度“t”变薄，当半导体晶片1被输送时，这不会产生任何问题。此后，通过进行等离子体蚀刻处理除去所有剩余的切割边缘区域（1c，3a）。

8. 发明申请

WO2006009286A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES AND APPARATUS THEREFORE 审中-公开
标题翻译：半导体器件及其设备的制造方法
公开(公告)号：WO2006009286A1
公开(公告)日：2006-01-26
申请号：PCT/JP2005/013673
申请日：2005-07-20
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , ARITA, Kiyoshi , HAJI, Hiroshi , NODA, Kazuhiro , NAKAGAWA, Akira , NISHINAKA, Teruaki
发明人： ARITA, Kiyoshi , HAJI, Hiroshi , NODA, Kazuhiro , NAKAGAWA, Akira , NISHINAKA, Teruaki
IPC分类号： H01L21/78
CPC分类号： G03F7/70433 , H01L21/78
摘要： With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.
摘要翻译：利用单元器件形成区域的二线段的长度尺寸作为布置间隔，在晶片上的器件形成有效区域中设置多条平行线，以便形成多个平行线分隔区域，单元器件形成区域与其他平行线分隔区域独立地并且与其它平行线分隔区域分开布置在每个并行线分隔区域中，使得获取单位元件形成区域的数量最大化，并且各个平行线分隔区域中的各个单位元件形成区域的布置被确定为整个器件形成有效的区域的布置，地区。

9. 发明申请

WO2005101943A3 ELECTRONIC COMPONENT MOUNTING APPARATUS AND METHOD OF MOUNTING ELECTRONIC COMPONENTS 审中-公开
标题翻译：电子元件安装装置和安装电子元件的方法
公开(公告)号：WO2005101943A3
公开(公告)日：2006-01-12
申请号：PCT/JP2005007276
申请日：2005-04-08
申请人： MATSUSHITA ELECTRIC IND CO LTD , HAJI HIROSHI , OZONO MITSURU
发明人： HAJI HIROSHI , OZONO MITSURU
IPC分类号： H01L21/52 , H01L21/00 , H01L21/68 , H01L21/683 , H05K13/00 , H05K13/04
CPC分类号： H01L21/67144 , H01L21/67132 , H01L21/681 , H01L21/6838 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/53039 , Y10T29/53174 , Y10T29/53178
摘要： In an electronic component mounting process for mounting electronic components (6) to a substrate (13), each of the electronic components (6) having an adhesive layer on a surface to be bonded to the substrate (13) is picked up with suction nozzle (33a) provided with individual heater (49), and a time taken for the mounting operation is so allotted that a first heating time (T1) of a duration from a moment when the suction nozzle (33a) comes into contact with the electronic component (6) for picking it up till another moment immediately before it begins a mounting motion to the substrate (13) is longer than a second heating time (T2) of a duration from the moment when the suction nozzle (33a) begins the mounting motion till another moment when it leaves the electronic component (6) mounted to the substrate (13).
摘要翻译：在将电子部件（6）安装到基板（13）的电子部件安装工序中，在与基板（13）接合的表面上具有粘接层的各电子部件（6）被吸引吸嘴（33a），设置有单独的加热器（49），并且分配用于安装操作的时间，使得从吸嘴（33a）与电子部件接触的时刻的持续时间的第一加热时间（T1）（6），用于将其拾取直到其开始向衬底（13）的安装运动之前的另一时刻长于从吸嘴（33a）开始安装运动的时刻开始的持续时间的第二加热时间（T2）直到其离开安装到基板（13）的电子部件（6）的另一时刻。

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