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1. 发明申请

WO2010057842A1 PREPARING A SURFACE OF A SAPPHIRE SUBSTRATE FOR FABRICATING HETEROSTRUCTURES 审中-公开
标题翻译：制备SAPPHIRE底物的表面以制备异体结构
公开(公告)号：WO2010057842A1
公开(公告)日：2010-05-27
申请号：PCT/EP2009/065202
申请日：2009-11-16
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , GAUDIN, Gweltaz , KENNARD, Mark , PICCIN, Matteo , RADU, Ionut , VAUFREDAZ, Alexandre
发明人： GAUDIN, Gweltaz , KENNARD, Mark , PICCIN, Matteo , RADU, Ionut , VAUFREDAZ, Alexandre
IPC分类号： H01L21/18 , H01L21/762
CPC分类号： H01L21/76256 , H01L21/187
摘要： The invention relates to a method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate, the method including a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. In accordance with the invention, the method includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100°C to 500°C.
摘要翻译：本发明涉及一种制造异质结构的方法，该方法至少包括由蓝宝石制成的第一衬底（120）和由具有不同于第一衬底的热膨胀系数的材料制成的第二衬底（110）方法包括在由蓝宝石制成的第一衬底（120）上分层结合第二衬底（110）的步骤（S6）。根据本发明，该方法包括在将两个基板结合在一起之前，将步骤（S1）在位于100℃至500℃范围内的温度下烘烤第一基板（120）。

2. 发明申请

WO2009112894A8 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
公开(公告)号：WO2009112894A8
公开(公告)日：2009-09-17
申请号：PCT/IB2008/052203
申请日：2008-03-13
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
发明人： ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
IPC分类号： H01L29/78
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10 10 charges/cm 2 . The invention also relates to a process for making such a substrate.

3. 发明申请

WO2012126752A1 APPARATUS AND A METHOD FOR DIRECT WAFER BONDING, MINIMIZING LOCAL DEFORMATION 审中-公开
标题翻译：装置和直接波形结合的方法，最小化局部变形
公开(公告)号：WO2012126752A1
公开(公告)日：2012-09-27
申请号：PCT/EP2012/054205
申请日：2012-03-12
申请人： SOITEC , GAUDIN, Gweltaz , BARTHELEMY, Alexandre
发明人： GAUDIN, Gweltaz , BARTHELEMY, Alexandre
IPC分类号： H01L21/67
CPC分类号： H01L21/67092 , H01L21/187
摘要： Apparatus is described for direct wafer bonding (200) together at least first and second wafers of circular shape, said second wafer having an initial bow. The apparatus includes annular support means (211) for receiving at least the second wafer. The annular suppor means (211) define a central recess (2111) in which the second wafer is free to deform under its own weight.
摘要翻译：描述了用于将至少第一和第二圆形晶片直接晶片接合（200）的装置，所述第二晶片具有初始弓形。该装置包括用于至少接收第二晶片的环形支撑装置（211）。环形支撑装置（211）限定中心凹部（2111），其中第二晶片在其自重下自由变形。

4. 发明申请

WO2013080010A1 PROCESS FOR FABRICATING A HETEROSTRUCTURE LIMITING THE FORMATION OF DEFECTS 审中-公开
标题翻译：制定限制形成缺陷的结构的方法
公开(公告)号：WO2013080010A1
公开(公告)日：2013-06-06
申请号：PCT/IB2012/002482
申请日：2012-11-21
申请人： SOITEC , GAUDIN, Gweltaz
发明人： GAUDIN, Gweltaz
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/02164 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02667 , H01L21/26513 , H01L21/30625 , H01L21/324 , H01L21/76254
摘要： The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising steps consisting in: - bonding a first substrate made of a single-crystal first material, said first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate;. - removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; - generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and - crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
摘要翻译：本发明涉及一种用于制造异质结构的方法，该方法包括由半导体制成的至少一个薄层和载体衬底，所述方法包括以下步骤： - 将由单晶第一材料制成的第一衬底接合，所述第一衬底包括由多晶第二材料制成的表层，到第二基板，从而在多晶层和第二基板之间形成接合界面。 - 从称为供体基板的一个基板的自由表面去除其厚度，使得仅保留薄层; - 通过所述多晶材料层的非晶化在所述第一基板和所述接合界面之间产生非晶半导体材料层; 以及 - 结晶所述非晶半导体材料层，所述新结晶层具有与相邻的第一衬底相同的取向。

5. 发明申请

WO2010057941A1 A METHOD OF PRODUCING A SILICON-ON-SAPPHIRE TYPE HETEROSTRUCTURE. 审中-公开
标题翻译：一种生产硅胶类型结构的方法。
公开(公告)号：WO2010057941A1
公开(公告)日：2010-05-27
申请号：PCT/EP2009/065440
申请日：2009-11-19
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , GAUDIN, Gweltaz , VAUFREDAZ, Alexandre , GUITTARD, Fleur
发明人： GAUDIN, Gweltaz , VAUFREDAZ, Alexandre , GUITTARD, Fleur
IPC分类号： H01L21/762
CPC分类号： H01L21/76256 , H01L21/2007
摘要： The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate (110) onto a sapphire substrate (120) and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate (110). In accordance with the method, grinding is carried out using a wheel (210) with a grinding surface (211) that comprises abrasive particles having a mean dimension of more than 6.7 urn; further, after grinding and before etching, said method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range 150 °C to 170 °C.
摘要翻译：本发明提供了一种制造蓝宝石型的异质结构的方法，包括将SOI衬底（110）接合到蓝宝石衬底（120）上并使SOI衬底变薄，通过研磨进行稀化，然后蚀刻 SOI衬底（110）。根据该方法，使用具有包括平均尺寸大于6.7μm的磨料颗粒的研磨表面（211）的轮（210）进行研磨; 此外，在研磨之后和蚀刻之前，所述方法包括在150℃至170℃的温度范围内对异质结构进行后磨削退火的步骤。

6. 发明申请

WO2010052151A1 SURFACE TREATMENT FOR MOLECULAR BONDING 审中-公开
标题翻译：表面处理分子结合
公开(公告)号：WO2010052151A1
公开(公告)日：2010-05-14
申请号：PCT/EP2009/064121
申请日：2009-10-27
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , CASTEX, Arnaud , GAUDIN, Gweltaz , BROEKAART, Marcel
发明人： CASTEX, Arnaud , GAUDIN, Gweltaz , BROEKAART, Marcel
IPC分类号： C03C15/00 , C03C17/22 , C03C27/06
CPC分类号： H01L21/31053 , H01L21/76256
摘要： A method of bonding a first substrate (210) on a second substrate (220) by molecular bonding, the method comprising the following steps: • forming a layer of insulation (212) on the bonding face (210a) of the first substrate (210); • chemical -mechanical polishing said layer of insulation (212); • activating the bonding surface of the second substrate (220) by plasma treatment; and • bonding together the two substrates (210, 220) by molecular bonding; the method being characterized in that it further comprises, after the chemical -mechanical polishing step and before the bonding step, a step of etching the surface (212a) of the layer of insulation (212) formed on the first substrate.
摘要翻译：一种通过分子键合将第一衬底（210）接合在第二衬底（220）上的方法，所述方法包括以下步骤：在第一衬底（210）的接合面（210a）上形成绝缘层（212））; °化学机械抛光所述绝缘层（212）; °通过等离子体处理激活第二基板（220）的接合表面; 和通过分子键合将两个基板（210,220）结合在一起; 该方法的特征在于，在化学机械抛光步骤之后并且在结合步骤之前还包括蚀刻形成在第一基板上的绝缘层（212）的表面（212a）的步骤。

7. 发明申请

WO2009150503A1 METHOD FOR PREPARING HYDROPHOBIC SURFACES 审中-公开
标题翻译：制备疏水表面的方法
公开(公告)号：WO2009150503A1
公开(公告)日：2009-12-17
申请号：PCT/IB2009/005791
申请日：2009-05-28
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , PECLARD, Nicolas , RADOUANE, Khalid , GAUDIN, Gweltaz , RADU, Ionut , KERDILES, Sébastien
发明人： PECLARD, Nicolas , RADOUANE, Khalid , GAUDIN, Gweltaz , RADU, Ionut , KERDILES, Sébastien
IPC分类号： H01L21/306 , H01L21/762
CPC分类号： H01L21/02046 , H01L21/76254
摘要： The invention relates to a method for preparing hydrophobic surfaces which find their application in direct silicon bonding and strained material layer growth. The method comprises providing a substrate and subjecting the substrate to a mixed plasma treatment, wherein the mixed plasma comprises a reducing gas plasma, in particular H2, and an inert gas plasma, in particular Ar and/or He.
摘要翻译：本发明涉及一种用于制备疏水性表面的方法，其可用于直接硅键合和应变材料层生长。该方法包括提供衬底并对衬底进行混合等离子体处理，其中混合等离子体包括还原气体等离子体，特别是H2，以及惰性气体等离子体，特别是Ar和/或He。

8. 发明申请

WO2009112894A1 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
标题翻译：具有绝缘层的充电区的基底
公开(公告)号：WO2009112894A1
公开(公告)日：2009-09-17
申请号：PCT/IB2008052203
申请日：2008-03-13
申请人： SOITEC SILICON ON INSULATOR , ALLIBERT FREDERIC , GAUDIN GWELTAZ , LALLEMENT FABRICE , LANDRU DIDIER , LANDRY KARINE , SHAHEEN MOHAMAD , MAZURE CARLOS
发明人： ALLIBERT FREDERIC , GAUDIN GWELTAZ , LALLEMENT FABRICE , LANDRU DIDIER , LANDRY KARINE , SHAHEEN MOHAMAD , MAZURE CARLOS
IPC分类号： H01L29/78
CPC分类号： H01L29/78603 , H01L29/32 , H01L29/7841 , H01L31/0248
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to a process for making such a substrate.
摘要翻译：本发明涉及一种基板，包括连续的基底晶片（1），绝缘层（2）和顶部半导体层（3），其特征在于绝缘层（2）至少包括电荷密度为绝对值高于1010电荷/ cm2。本发明还涉及制造这种基材的方法。

9. 发明申请

WO2009101495A1 PROCESSING FOR BONDING TWO SUBSTRATES 审中-公开
标题翻译：用于连接两个基板的处理
公开(公告)号：WO2009101495A1
公开(公告)日：2009-08-20
申请号：PCT/IB2009/000142
申请日：2009-01-23
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , GAUDIN, Gweltaz , LALLEMENT, Fabrice , COLNAT, Cyrille , GIARD, Pascale
发明人： GAUDIN, Gweltaz , LALLEMENT, Fabrice , COLNAT, Cyrille , GIARD, Pascale
IPC分类号： H01L21/18 , H01L21/762
CPC分类号： H01L21/187 , H01L21/67092 , H01L21/76251 , Y10T156/10
摘要： The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates The invention also relates to a corresponding bonding equipment
摘要翻译：本发明涉及一种用于接合两个基板，特别是两个半导体基板的方法，为了能够提高该工艺的可靠性，提供了在基板的接合表面上提供气流的步骤。本发明还涉及到相应的粘合设备

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