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1. 发明申请

WO2011066035A2 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：用于减少谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：WO2011066035A2
公开(公告)日：2011-06-03
申请号：PCT/US2010/050805
申请日：2010-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOTULA, Alan, B. , ELLIS-MONAGHAN, John, J. , JOSEPH, Alvin, J. , LEVY, Max, G. , PHELPS, Richard, A. , SLINKMAN, James, A.
发明人： BOTULA, Alan, B. , ELLIS-MONAGHAN, John, J. , JOSEPH, Alvin, J. , LEVY, Max, G. , PHELPS, Richard, A. , SLINKMAN, James, A.
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）在绝缘体层上的半导体结构（100）。衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。此外，紧邻绝缘体层的半导体衬底的一部分（102）可掺杂相同掺杂剂（111）的略高的剂量，具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了所得到的寄生电容器的阈值电压（Vt），从而降低了谐波特性。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

2. 发明申请

WO2012018664A1 METHOD, APPARATUS, AND DESIGN STRUCTURE FOR SILICON-ON- INSULATOR HIGH-BANDWIDTH CIRCUITRY WITH REDUCED CHARGE LAYER 审中-公开
标题翻译：具有减少充电层的绝缘子绝缘子高带宽电路的方法，装置和设计结构
公开(公告)号：WO2012018664A1
公开(公告)日：2012-02-09
申请号：PCT/US2011/045640
申请日：2011-07-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOTULA, Alan, B. , JOSEPH, Alvin, J. , SLINKMAN, James, A. , WOLF, Randy, L.
发明人： BOTULA, Alan, B. , JOSEPH, Alvin, J. , SLINKMAN, James, A. , WOLF, Randy, L.
IPC分类号： H01L21/762 , H01L21/84 , H01L27/02 , H01L27/06 , H01L27/12
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/0211 , H01L27/0617 , H01L27/1203
摘要： A method, integrated circuit and design structure includes a silicon substrate layer (102) having trench structures (106) and an ion impurity implant (108). An insulator layer (110) is positioned on and contacts the silicon substrate layer. The insulator layer (110) fills the trench structures (106). A circuitry layer is positioned on and contacts the buried insulator layer (110). The circuitry layer comprises groups of active circuits (112) separated by passive structures (114). The trench structures (106) are positioned between the groups of active circuits (112) when the integrated circuit structure is viewed from the top view. Thus, the trench structures (106) are below the passive structures (114) and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
摘要翻译：一种方法，集成电路和设计结构包括具有沟槽结构（106）和离子杂质注入（108）的硅衬底层（102）。绝缘体层（110）位于硅衬底层上并接触硅衬底层。绝缘体层（110）填充沟槽结构（106）。电路层位于埋入的绝缘体层（110）上并与其接触。电路层包括由被动结构（114）分离的一组有源电路（112）。当从顶视图观察集成电路结构时，沟槽结构（106）位于有源电路组（112）之间。因此，当从顶视图观察集成电路结构时，沟槽结构（106）在无源结构（114）下方并且不在电路组下方。

3. 发明申请

WO2010075051A1 BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH 审中-公开
标题翻译：用于SOI无线电频率开关的偏置电压发生电路
公开(公告)号：WO2010075051A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/067968
申请日：2009-12-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOTULA, Alan, B. , NOWAK, Edward, J.
发明人： BOTULA, Alan, B. , NOWAK, Edward, J.
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L27/0218 , H01P1/15 , H03K17/693 , H03K2217/0018
摘要： A radio frequency (RF) switch (40/42/44) located on a semiconductor-on-insulator (SOI) substrate (10/20/30) includes at least one electrically biased region (13) in a bottom semiconductor layer (10). The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna (FIG. 3). The electrically biased region may be biased (18/79/94 or 28/89/99) to eliminate or reduce an accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal (FIG. 6). The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.
摘要翻译：位于绝缘体上半导体（SOI）衬底（10/20/30）上的射频（RF）开关（40/42/44）包括底部半导体层（10）中的至少一个电偏置区域）。 RF开关从功率放大器接收RF信号并将RF信号发射到天线（图3）。电偏置区域可以被偏置（18/79/94或28/89/99）以消除或减少积聚区域，以稳定耗尽区域和/或防止在底部半导体层中形成反转区域，从而减少由RF信号引起的寄生耦合和谐波产生。分压器电路和整流电路产生至少一个幅度随RF信号幅度变化的偏置电压（图6）。将至少一个偏置电压施加到至少一个电偏置区域，以保持底部半导体层的适当偏置，以最小化寄生耦合，信号损耗和谐波产生。

4. 发明申请

WO2013085617A1 FORMING STRUCTURES ON RESISTIVE SUBSTRATES 审中-公开
标题翻译：形成电阻基板的结构
公开(公告)号：WO2013085617A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/059428
申请日：2012-10-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BOTULA, Alan, B. , CAMILLO-CASTILLO, Renata , DUNN, James, S. , GAMBINO, Jeffrey, P. , HERSHBERGER, Douglas, B. , JOSEPH, Alvin, J. , RASSEL, Robert, M. , STIDHAM, Mark, E.
IPC分类号： H01L27/02 , H01L27/102 , H01L27/105
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate (100) includes a first region (126) having a first resistivity, for optimizing a field effect transistor (101), a second region(128) having a second resistivity, for optimizing an npn subcollector (116) of a bipolar transistor device (111) and triple well (114,116), a third region(112) having a third resistivity, with a high resistivity for a passive device, a fourth region (151), substantially without implantation, to provide low perimeter capacitance (105) for devices.
摘要翻译：衬底（100）包括具有第一电阻率的第一区域（126），用于优化场效应晶体管（101），具有第二电阻率的第二区域（128），用于优化双极晶体管的npn子集电极（116）装置（111）和三阱（114,116），具有第三电阻率的第三区域（112），具有用于无源器件的高电阻率，基本上没有植入的第四区域（151），以提供低周边电容（105）用于设备。

5. 发明申请

WO2014077936A2 COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE 审中-公开
标题翻译：补偿硅衬底中的电荷
公开(公告)号：WO2014077936A2
公开(公告)日：2014-05-22
申请号：PCT/US2013/057962
申请日：2013-09-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BOTULA, Alan, B. , JAFFE, Mark, D. , JOSEPH, Alvin, J. , PHELPS, Richard, A. , SLINKMAN, James , WOLF, Randy, L.
IPC分类号： H01L29/16 , H01L21/66
CPC分类号： H01L29/0603 , H01L21/26513 , H01L21/7624 , H01L21/84 , H01L22/14 , H01L22/20 , H01L27/1203 , H01L29/16 , H01L2924/0002 , H01L2924/00
摘要： A silicon device 100 includes an active silicon layer 106, a buried oxide (BOX) layer 104 beneath the active silicon layer 106 and a high-resistivity silicon layer 102 beneath the BOX layer. The device also includes a harmonic suppression layer 110 at a boundary of the BOX layer 104 and the high-resistivity silicon layer 102.
摘要翻译：硅器件100包括有源硅层106，位于有源硅层106下方的埋入氧化物（BOX）层104和位于BOX层下面的高电阻率硅层102。该器件还包括在BOX层104和高电阻率硅层102的边界处的谐波抑制层110.

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