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1. 发明申请

WO2014031129A1 SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR 审中-公开
标题翻译：在矢量处理器中数据提取的系统和方法
公开(公告)号：WO2014031129A1
公开(公告)日：2014-02-27
申请号：PCT/US2012/052328
申请日：2012-08-24
申请人： QUALCOMM INCORPORATED , FRIDMAN, Jose , INGLE, Ajay Anant , MATHEW, Deepak , HOFFMAN, Marc, M. , LOPEZ, Michael, John
发明人： FRIDMAN, Jose , INGLE, Ajay Anant , MATHEW, Deepak , HOFFMAN, Marc, M. , LOPEZ, Michael, John
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
摘要翻译：公开了一种向量处理器中数据提取的系统和方法。在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的寄存器复制到存储器。

2. 发明申请

WO2010102134A1 APPARATUS AND METHOD TO TRANSLATE VIRTUAL ADDRESSES TO PHYSICAL ADDRESSES IN A BASE PLUS OFFSET ADDRESSING MODE 审中-公开
标题翻译：将虚拟地址转换为基本偏移寻址模式的物理地址的装置和方法
公开(公告)号：WO2010102134A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026249
申请日：2010-03-04
申请人： QUALCOMM INCORPORATED , BASSETT, Paul, Douglas , INGLE, Ajay, Anant , JAMIL, Sujat , CODRESCU, Lucian , AHMED, Muhammad
发明人： BASSETT, Paul, Douglas , INGLE, Ajay, Anant , JAMIL, Sujat , CODRESCU, Lucian , AHMED, Muhammad
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

3. 发明申请

WO2009158269A1 MEMORY MANAGEMENT UNIT DIRECTED ACCESS TO SYSTEM INTERFACES 审中-公开
标题翻译：内存管理单元指导访问系统界面
公开(公告)号：WO2009158269A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/047795
申请日：2009-06-18
申请人： QUALCOMM INCORPORATED , INGLE, Ajay, Anant , KOOB, Christopher, Edward
发明人： INGLE, Ajay, Anant , KOOB, Christopher, Edward
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
摘要翻译：描述了用于维护来自一个或多个处理器线程的事务请求的存储器管理单元（MMU）。 MMU可以包括翻译后备缓冲器（TLB）。 TLB可以包括存储模块和逻辑电路。存储模块可以存储指示多个接口之一的位。该位可以与物理地址范围相关联。逻辑电路可以将物理地址范围内的物理地址路由到多个接口之一。

4. 发明申请

WO2011109476A1 SYSTEM AND METHOD OF PROCESSING HIERARCHICAL VERY LONG INSTRUCTION PACKETS 审中-公开
标题翻译：处理分层非常长的指令包的系统和方法
公开(公告)号：WO2011109476A1
公开(公告)日：2011-09-09
申请号：PCT/US2011/026815
申请日：2011-03-02
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
发明人： CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3853 , G06F9/30149
摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.
摘要翻译：公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。在特定实施例中，公开了一种处理指令的方法。该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。响应于确定指令包括子分组，该方法还包括执行每个子指令。

5. 发明申请

WO2007056675A3 ARITHMETHIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR 审中-公开
公开(公告)号：WO2007056675A3
公开(公告)日：2007-05-18
申请号：PCT/US2006/060500
申请日：2006-11-02
申请人： QUALCOMM INCORPORATED , AHMED, Muhammad , INGLE, Ajay Anant , JAMIL, Sujat
发明人： AHMED, Muhammad , INGLE, Ajay Anant , JAMIL, Sujat
IPC分类号： G06F9/355
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

6. 发明申请

WO2006128079A3 LOW POWER MICROPROCESSOR CACHE MEMORY AND METHOD OF OPERATION 审中-公开
标题翻译：低功耗微处理器高速缓存存储器和操作方法
公开(公告)号：WO2006128079A3
公开(公告)日：2007-02-08
申请号：PCT/US2006020640
申请日：2006-05-25
申请人： QUALCOMM INC , MOHAMMAD BAKER , AHMED MUHAMMAD , BASSETT PAUL , JAMIL SUJAT , INGLE AJAY ANANT
发明人： MOHAMMAD BAKER , AHMED MUHAMMAD , BASSETT PAUL , JAMIL SUJAT , INGLE AJAY ANANT
IPC分类号： G06F12/08 , G11C15/04
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.
摘要翻译：用于处理包括使用数字信号处理器的通信（例如，CDMA）系统中的传输的技术。数字信号处理器包括高速缓冲存储器系统，并将多个高速缓存存储器匹配线与可寻址存储器的可寻址存储器线相关联。每个高速缓存存储器匹配行与高速缓冲存储器的相应组中的一个相关联。该方法和系统将每个高速缓冲存储器匹配线保持在低电压。一旦数字信号处理器启动对高速缓冲存储器的搜索，以从相应的高速缓冲存储器组中的选定的一个中选出一个数据，则匹配线驱动电路将高速缓冲存储器匹配线之一从低电压驱动到高电压。高速缓存存储器匹配行中所选择的一个对应于高速缓冲存储器的所选择的相应组中的一个。数字信号处理器将所选择的一个高速缓冲存储器匹配线与可寻址存储器线中的相关联的一个进行比较。在比较步骤之后，该过程将高速缓存存储器匹配行之一返回到低电压。

7. 发明申请

WO2013049765A1 FIFO LOAD INSTRUCTION 审中-公开
标题翻译： FIFO加载指令
公开(公告)号：WO2013049765A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058181
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , ZENG, Mao , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant
发明人： ZENG, Mao , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
摘要翻译：指令识别寄存器和存储器位置。在由处理器执行指令时，从存储器位置加载一个物品，并执行移位和插入操作以移位寄存器中的数据并将该项目插入到寄存器中。

8. 发明申请

WO2009032936A1 SYSTEM AND METHOD OF EXECUTING INSTRUCTIONS IN A MULTI-STAGE DATA PROCESSING PIPELINE 审中-公开
标题翻译：在多级数据处理管道中执行指令的系统和方法
公开(公告)号：WO2009032936A1
公开(公告)日：2009-03-12
申请号：PCT/US2008/075270
申请日：2008-09-04
申请人： QUALCOMM Incorporated , INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
发明人： INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.
摘要翻译：公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。该装置还包括耦合到指令执行管线的控制逻辑电路。控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。控制逻辑电路还适于在执行解码的指令期间执行至少一个非跳过级。

9. 发明申请

WO2013013100A1 TABLE CALL INSTRUCTION FOR FREQUENTLY CALLED FUNCTIONS 审中-公开
标题翻译：表呼叫功能的常用功能
公开(公告)号：WO2013013100A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/047488
申请日：2012-07-19
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich, James , CODRESCU, Lucian , TABONY, Charles, Joseph , INGLE, Ajay, Anant , VENKUMAHANTI, Suresh, K. , MENEZES, Evandro, Carlos
发明人： PLONDKE, Erich, James , CODRESCU, Lucian , TABONY, Charles, Joseph , INGLE, Ajay, Anant , VENKUMAHANTI, Suresh, K. , MENEZES, Evandro, Carlos
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30167 , G06F9/30181 , G06F9/322 , G06F9/327
摘要： An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.
摘要翻译：一种装置包括存储包含操作码和操作数的指令的存储器。操作数指定存储立即值的寄存器的立即值或寄存器指示符。立即值可用于标识函数调用地址。功能调用地址可以从多个功能调用地址中选择。

10. 发明申请

WO2012061417A1 ARCHITECTURE AND METHOD FOR ELIMINATING STORE BUFFERS IN A DSP/PROCESSOR WITH MULTIPLE MEMORY ACCESSES 审中-公开
标题翻译：在具有多个存储器访问的DSP /处理器中消除存储缓冲区的架构和方法
公开(公告)号：WO2012061417A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/058824
申请日：2011-11-01
申请人： QUALCOMM Incorporated , LIN, Jentsung Ken , INGLE, Ajay Anant , KUO, Eai-hsin A. , BASSETT, Paul Douglas
发明人： LIN, Jentsung Ken , INGLE, Ajay Anant , KUO, Eai-hsin A. , BASSETT, Paul Douglas
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3857
摘要： A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.
摘要翻译：一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。当至少一个指令不能在架构上完成时，延迟两个指令。当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。评估延迟足以评估两种指令是否可以在架构上完成。评估延迟可以输入到写入控制，而不是存储器的读取控制。可以调整存储器的预充电时钟以考虑评估延迟。评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。

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