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1. 发明申请

WO2007029169A2 PROCESSOR ARRAY WITH SEPARATE SERIAL MODULE 审中-公开
标题翻译：处理器阵列与单独的串行模块
公开(公告)号：WO2007029169A2
公开(公告)日：2007-03-15
申请号：PCT/IB2006/053102
申请日：2006-09-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KLEIHORST, Richard, P. , ABBO, Anteneh, A. , CHOUDHARY, Vishal
发明人： KLEIHORST, Richard, P. , ABBO, Anteneh, A. , CHOUDHARY, Vishal
CPC分类号： G06F15/8015
摘要： A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines of data input to the module (30) serially. Processing can continue in the processor elements (2) in parallel using suitable programming steps.
摘要翻译：处理器阵列具有处理器元件（2）和存储器（4），并行连接到可由处理器元件（2）并行访问的处理器元件（2）和存储器（4）。单独的串行模块（30）例如以查找表模块（30）的形式提供附加功能。串行模块（3）串行地处理输入到模块（30）的数据线。处理可以在处理器元件（2）中并行使用合适的编程步骤继续。

2. 发明申请

WO2005088424A3 CALIBRATION OF CLOCK GENERATORS IN SYSTEM-ON-CHIP INTEGRATED CIRCUITS 审中-公开
标题翻译：系统在芯片集成电路中的时钟发生器校准
公开(公告)号：WO2005088424A3
公开(公告)日：2006-03-02
申请号：PCT/IB2005050726
申请日：2005-02-28
申请人： KONINKL PHILIPS ELECTRONICS NV , CHOUDHARY VISHAL S , KATOCH ATUL
发明人： CHOUDHARY VISHAL S , KATOCH ATUL
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/04 , G06F1/10
摘要： In a GALS based integrated circuit, the ring oscillator (400) with a programmable delay line (500), which can be configured for different delays using a control word (600). Scan patterns are loaded into the N modules at the respective launching flip-flops (100) and the resultant signal value captured by the capture flip-flops is output to a register (700). The resultant signature of values is compared with a valid signature (800). If it does not match, the delay of the ring oscillator (400) is changed by the control word (600), and the path delay test is carried out again. This process is repeated until the resultant signature (700) matches the valid signature (800) at which time, the calibration process is complete.
摘要翻译：在基于GALS的集成电路中，具有可编程延迟线（500）的环形振荡器（400），其可以被配置用于使用控制字（600）的不同延迟。在相应的发射触发器（100）将扫描模式加载到N个模块中，并且由捕获触发器捕获的合成信号值被输出到寄存器（700）。将所得到的值的签名与有效签名进行比较（800）。如果不匹配，则通过控制字（600）改变环形振荡器（400）的延迟，并再次执行路径延迟测试。重复该过程直到合成签名（700）与有效签名（800）匹配，此时校准过程完成。

3. 发明申请

WO2005088424A2 CALIBRATION OF CLOCK GENERATORS IN SYSTEM-ON-CHIP INTEGRATED CIRCUITS 审中-公开
标题翻译：系统在芯片集成电路中的时钟发生器校准
公开(公告)号：WO2005088424A2
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050726
申请日：2005-02-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , CHOUDHARY, Vishal, S. , KATOCH, Atul
发明人： CHOUDHARY, Vishal, S. , KATOCH, Atul
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/10
摘要： In a GALS based integrated circuit, the ring oscillator (400) with a programmable delay line (500), which can be configured for different delays using a control word (600). Scan patterns are loaded into the N modules at the respective launching flip-flops (100) and the resultant signal value captured by the capture flip-flops is output to a register (700). The resultant signature of values is compared with a valid signature (800). If it does not match, the delay of the ring oscillator (400) is changed by the control word (600), and the path delay test is carried out again. This process is repeated until the resultant signature (700) matches the valid signature (800) at which time, the calibration process is complete. Advantages of the present invention include: Accuracy - since on-chip real critical paths are used for measuring the delays, the clock generators can be fine-tuned to run at optimal operating frequency (closest to the maximum possible frequency); and - Simplicity - the proposed solution has no major costs in terms of silicon area; it uses existing tools (for generating test patterns for activating critical paths in a circuit) and minimum hardware for calibration.
摘要翻译：在基于GALS的集成电路中，具有可编程延迟线（500）的环形振荡器（400），其可以被配置用于使用控制字（600）的不同延迟。在相应的发射触发器（100）将扫描模式加载到N个模块中，并且由捕获触发器捕获的合成信号值被输出到寄存器（700）。将所得到的值的签名与有效签名进行比较（800）。如果不匹配，则通过控制字（600）改变环形振荡器（400）的延迟，并再次执行路径延迟测试。重复该过程直到合成签名（700）与有效签名（800）匹配，此时校准过程完成。本发明的优点包括：精度 - 由于使用片上实际关键路径来测量延迟，所以时钟发生器可被微调以在最佳工作频率（最接近最大可能频率）运行; 和 - 简单 - 提出的解决方案在硅面积方面没有重大的成本; 它使用现有工具（用于生成用于激活电路中的关键路径的测试模式）和用于校准的最低硬件。

4. 发明申请

WO2007135635A9 INTEGRATED CIRCUIT ARRANGEMENT FOR CARRYING OUT BLOCK AND LINE BASED PROCESSING OF IMAGE DATA 审中-公开
标题翻译：集成电路布局，用于实现块和线性图像处理
公开(公告)号：WO2007135635A9
公开(公告)日：2008-02-14
申请号：PCT/IB2007051882
申请日：2007-05-16
申请人： NXP BV , KLEIHORST RICHARD P , ABBO ANTENEH A , CHOUDHARY VISHAL
发明人： KLEIHORST RICHARD P , ABBO ANTENEH A , CHOUDHARY VISHAL
IPC分类号： G06T1/60 , G06F7/78 , G06F15/80 , G06T1/20 , H04N7/26
CPC分类号： G06F15/8007 , H04N19/423 , H04N19/436 , H04N19/60
摘要： An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.
摘要翻译：集成电路装置具有处理器阵列（2），处理器阵列（4）和存储器（6），存储器元件（8）以行（32）和列（30）排列。存储器元件（8）的列（30）由相应的处理器元件（4）寻址。输入定序器（14）和反馈路径（24）协作以重新排列存储器（6）中的输入数据以执行基于块和行的处理。

5. 发明申请

WO2007135635A1 INTEGRATED CIRCUIT ARRANGEMENT FOR CARRYING OUT BLOCK AND LINE BASED PROCESSING OF IMAGE DATA 审中-公开
标题翻译：集成电路布局，用于实现块和线性图像处理
公开(公告)号：WO2007135635A1
公开(公告)日：2007-11-29
申请号：PCT/IB2007/051882
申请日：2007-05-16
申请人： NXP B.V. , KLEIHORST, Richard, P. , ABBO, Anteneh, A. , CHOUDHARY, Vishal
发明人： KLEIHORST, Richard, P. , ABBO, Anteneh, A. , CHOUDHARY, Vishal
IPC分类号： G06T1/60 , G06F7/78 , H04N7/26 , G06T1/20 , G06F15/80
CPC分类号： G06F15/8007 , H04N19/423 , H04N19/436 , H04N19/60
摘要： An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.
摘要翻译：集成电路装置具有处理器阵列（2），处理器阵列（4）和存储器（6），存储器元件（8）以行（32）和列（30）排列。存储器元件（8）的列（30）由相应的处理器元件（4）寻址。输入定序器（14）和反馈路径（24）协作以重新排列存储器（6）中的输入数据以执行基于块和行的处理。

6. 发明申请

WO2007029169A3 PROCESSOR ARRAY WITH SEPARATE SERIAL MODULE 审中-公开
标题翻译：处理器阵列与单独的串行模块
公开(公告)号：WO2007029169A3
公开(公告)日：2007-07-05
申请号：PCT/IB2006053102
申请日：2006-09-04
申请人： KONINKL PHILIPS ELECTRONICS NV , KLEIHORST RICHARD P , ABBO ANTENEH A , CHOUDHARY VISHAL
发明人： KLEIHORST RICHARD P , ABBO ANTENEH A , CHOUDHARY VISHAL
IPC分类号： G06F15/80
CPC分类号： G06F15/8015
摘要： A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines of data input to the module (30) serially. Processing can continue in the processor elements (2) in parallel using suitable programming steps.
摘要翻译：处理器阵列具有并行连接到由处理器元件（2）并行访问的处理器元件（2）和存储器（4）。单独的串行模块（30）提供例如以查询表模块（30）的形式的附加功能。串行模块（3）串行地输入到模块（30）的数据行。处理可以在处理器元件（2）中并行使用合适的编程步骤继续进行。

7. 发明申请

WO2006000929A3 POWER MANAGEMENT 审中-公开
标题翻译：能源管理
公开(公告)号：WO2006000929A3
公开(公告)日：2006-03-30
申请号：PCT/IB2005051875
申请日：2005-06-08
申请人： KONINKL PHILIPS ELECTRONICS NV , ABBO ANTENEH A , CHOUDHARY VISHAL
发明人： ABBO ANTENEH A , CHOUDHARY VISHAL
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), ,PE(N)), each processor ((PE(0), PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronise the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronisation signals generated by the control processor (16), thereby minimising the power consumption of the SIMD processor architecture (2).
摘要翻译：提供了一种用于处理数据向量流的SIMD处理器架构（2），该架构包括包括多个处理器（PE（0），PE（N））的处理器阵列（4），每个处理器 0），PE（N））适于处理每个向量中的数据元素，处理器阵列（4）的操作由具有第一频率的本地时钟信号控制;控制处理器（16），其适于控制操作SIMD处理器架构（2）并产生信号以使处理器阵列（4）的操作与数据矢量流同步，控制处理器（16）的操作由具有第二频率的本地时钟信号控制 ;以及用于响应于由控制处理器（16）产生的同步信号调整本地时钟信号的频率的功率管理装置（30），从而最小化SIMD处理器体系结构（2）的功耗。

8. 发明申请

WO2006000929A2 POWER MANAGEMENT 审中-公开
标题翻译：能源管理
公开(公告)号：WO2006000929A2
公开(公告)日：2006-01-05
申请号：PCT/IB2005/051875
申请日：2005-06-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ABBO, Anteneh, A. , CHOUDHARY, Vishal
发明人： ABBO, Anteneh, A. , CHOUDHARY, Vishal
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A SIMD processor architecture for processing a stream of data vectors is provided, the architecture comprising a processor array comprising a plurality of processors, each processor being adapted to process a data element in each vector, the operation of the processor array being controlled by a local clock signal having a first frequency; a control processor adapted to control the operation of the SIMD processor architecture and generate signals to synchronise the operation of the processor array with the stream of data vectors, the operation of the control processor being controlled by a local clock signal having a second frequency; and power management means for adjusting the frequencies of the local clock signals in response to the synchronisation signals generated by the control processor, thereby minimising the power consumption of the SIMD processor architecture.
摘要翻译：提供了一种用于处理数据向量流的SIMD处理器架构，该架构包括包括多个处理器的处理器阵列，每个处理器适于处理每个向量中的数据元素，处理器阵列的操作由本地时钟信号具有第一频率; 控制处理器，其适于控制SIMD处理器架构的操作并且产生信号以使处理器阵列的操作与数据向量流同步，所述控制处理器的操作由具有第二频率的本地时钟信号控制; 以及用于响应于由控制处理器产生的同步信号来调整本地时钟信号的频率的功率管理装置，由此最小化SIMD处理器架构的功耗。

9. 发明申请

WO2003100601A3 CONFIGURABLE PROCESSOR 审中-公开
公开(公告)号：WO2003100601A3
公开(公告)日：2003-12-04
申请号：PCT/IB2003/001731
申请日：2003-04-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DE OLIVEIRA KASTRUP PEREIRA, Bernardo , CHOUDHARY, Vishal, S.
发明人： DE OLIVEIRA KASTRUP PEREIRA, Bernardo , CHOUDHARY, Vishal, S.
IPC分类号： G06F9/38
摘要： A processor comprises a main controller (CTR11) and a plurality of processing units (1 - 9). Each processing unit (1 - 9) has a local controller (CTR1 - CTR9) and at least one functional unit (FU1 - FU9) controllable by the local controller (CTR1 - CTR9). The local controller (CTR1 - CTR9) of a processing unit (1 - 9) is coupled (15) to the main controller (CTR11). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit (1 - 9). The main controller (CTR11) is arranged to process the at least one instruction for increasing the activity of at least one processing unit (1 - 9). One or more processing units (1 - 9) of the processor can be completely switched off, including the corresponding local controller (CTR1 - CTR9), since the instructions for switching on a processing unit (1 - 9) are not processed by the corresponding local controller (CTR1 - CTR9), but by the main controller (CTR11) itself.

10. 发明申请

WO2003100601A2 CONFIGURABLE PROCESSOR 审中-公开
标题翻译：可配置处理器
公开(公告)号：WO2003100601A2
公开(公告)日：2003-12-04
申请号：PCT/IB2003/001731
申请日：2003-04-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DE OLIVEIRA KASTRUP PEREIRA, Bernardo , CHOUDHARY, Vishal, S.
发明人： DE OLIVEIRA KASTRUP PEREIRA, Bernardo , CHOUDHARY, Vishal, S.
IPC分类号： G06F9/38
CPC分类号： G06F9/30083 , G06F9/3885
摘要： A processor comprises a main controller (CTR11) and a plurality of processing units (1 - 9). Each processing unit (1 - 9) has a local controller (CTR1 - CTR9) and at least one functional unit (FU1 - FU9) controllable by the local controller (CTR1 - CTR9). The local controller (CTR1 - CTR9) of a processing unit (1 - 9) is coupled (15) to the main controller (CTR11). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit (1 - 9). The main controller (CTR11) is arranged to process the at least one instruction for increasing the activity of at least one processing unit (1 - 9). One or more processing units (1 - 9) of the processor can be completely switched off, including the corresponding local controller (CTR1 - CTR9), since the instructions for switching on a processing unit (1 - 9) are not processed by the corresponding local controller (CTR1 - CTR9), but by the main controller (CTR11) itself.
摘要翻译：处理器包括主控制器（CTR11）和多个处理单元（1-9）。每个处理单元（1至9）具有本地控制器（CTR1-CTR9）和至少一个由本地控制器（CTR1-CTR9）控制的功能单元（FU1-FU9）。处理单元（1-9）的本地控制器（CTR1-CTR9）被耦合（15）到主控制器（CTR11）。处理器还包括指令集，其具有用于增加至少一个处理单元（1-9）的活动的至少一个指令。主控制器（CTR11）被布置成处理用于增加至少一个处理单元（1-9）的活动的至少一个指令。由于处理单元（1-9）的接通指令不被对应的处理单元（1〜9）处理，处理器的一个或多个处理单元（1〜9）可以完全关闭，包括相应的本地控制器（CTR1-CTR9）本地控制器（CTR1 - CTR9），但由主控制器（CTR11）本身。

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