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1. 发明申请

WO2005088424A3 CALIBRATION OF CLOCK GENERATORS IN SYSTEM-ON-CHIP INTEGRATED CIRCUITS 审中-公开
标题翻译：系统在芯片集成电路中的时钟发生器校准
公开(公告)号：WO2005088424A3
公开(公告)日：2006-03-02
申请号：PCT/IB2005050726
申请日：2005-02-28
申请人： KONINKL PHILIPS ELECTRONICS NV , CHOUDHARY VISHAL S , KATOCH ATUL
发明人： CHOUDHARY VISHAL S , KATOCH ATUL
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/04 , G06F1/10
摘要： In a GALS based integrated circuit, the ring oscillator (400) with a programmable delay line (500), which can be configured for different delays using a control word (600). Scan patterns are loaded into the N modules at the respective launching flip-flops (100) and the resultant signal value captured by the capture flip-flops is output to a register (700). The resultant signature of values is compared with a valid signature (800). If it does not match, the delay of the ring oscillator (400) is changed by the control word (600), and the path delay test is carried out again. This process is repeated until the resultant signature (700) matches the valid signature (800) at which time, the calibration process is complete.
摘要翻译：在基于GALS的集成电路中，具有可编程延迟线（500）的环形振荡器（400），其可以被配置用于使用控制字（600）的不同延迟。在相应的发射触发器（100）将扫描模式加载到N个模块中，并且由捕获触发器捕获的合成信号值被输出到寄存器（700）。将所得到的值的签名与有效签名进行比较（800）。如果不匹配，则通过控制字（600）改变环形振荡器（400）的延迟，并再次执行路径延迟测试。重复该过程直到合成签名（700）与有效签名（800）匹配，此时校准过程完成。

2. 发明申请

WO2004100376A9 BUFFER CIRCUIT 审中-公开
标题翻译：缓冲电路
公开(公告)号：WO2004100376A9
公开(公告)日：2005-11-17
申请号：PCT/IB2004050613
申请日：2004-05-07
申请人： KONINKL PHILIPS ELECTRONICS NV , KATOCH ATUL , JAIN SANJEEV K , MEIJER RINZE I M P
发明人： KATOCH ATUL , JAIN SANJEEV K , MEIJER RINZE I M P
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/00361 , H03K19/0027
摘要： A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.
摘要翻译：缓冲电路（31）例如用于片上总线的信号线的中继器或接收器电路接收输入信号，并产生输出信号。缓冲电路（31）包括第一反相级（7）和第二反相器级（9）。第二反相级（9）为输出（5）提供驱动。第一反相级（7）具有用于控制上拉路径和下拉路径的强度的附加电路（15,17,19,21,23,25,27,29）。根据一个或多个攻击者信号的状态来动态地控制上拉/下拉路径。在一个实施例中，切换阈值仅在最差情况下延迟情况下降低，即当信号线（3）与侵略者信号处于不同的逻辑电平时。在另一个实施例中，当信号线和侵扰器信号都处于相同的逻辑电平时，开关阈值升高，从而减少串扰。

3. 发明申请

WO2004021100A3 CURRENT MODE SIGNALLING IN ELECTRONIC DATA PROCESSING CIRCUIT 审中-公开
标题翻译：电子数据处理电路中的电流模式信号
公开(公告)号：WO2004021100A3
公开(公告)日：2006-03-02
申请号：PCT/IB0303390
申请日：2003-07-31
申请人： KONINKL PHILIPS ELECTRONICS NV , KATOCH ATUL , SEEVINCK EVERT , VEENDRICK HENDRICUS J M
发明人： KATOCH ATUL , SEEVINCK EVERT , VEENDRICK HENDRICUS J M
IPC分类号： G06F1/00 , H04L25/02 , H04L25/08
CPC分类号： H04L25/08 , H04L25/026 , H04L25/0272 , H04L25/0294
摘要： An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.
摘要翻译：电子数据处理电路在通信导体上使用电流模式信号，其中接收器向通信导体提供电流以尝试并保持导体上的电压恒定并且测量所需的电流。转换编码电路耦合在数据源电路和通信导体之间，用于响应于逻辑信号中的转换和在脉冲之外的第二状态以脉冲方式驱动通信导体处于第一状态。选择用于指示没有变化的电平，所以当没有发出变化时，接收器需要提供的电流比发出变化时更小。当没有变化时，最好只需要几乎零静态电流。

4. 发明申请

WO2007093935A3 DATA COMMUNICATION METHOD, DATA TRANSMISSION AND RECEPTION DEVICE AND SYSTEM 审中-公开
标题翻译：数据通信方法，数据传输和接收设备和系统
公开(公告)号：WO2007093935A3
公开(公告)日：2007-11-01
申请号：PCT/IB2007050397
申请日：2007-02-06
申请人： NXP BV , SVANELL KARL O , BOIJORT DANIEL J , KATOCH ATUL
发明人： SVANELL KARL O , BOIJORT DANIEL J , KATOCH ATUL
IPC分类号： H04L25/493
CPC分类号： H04L25/493
摘要： A method (100) is disclosed for communicating data over a data communication bus (310) comprising a first conductor (312) and a set of further conductors (314). The method (300) comprises providing the first conductor (312) with a first signal transition (210) for signalling the start of a first data communication period (T1 ); and providing a further conductor (314), after a predefined delay with respect to the provision of the first signal transition (210), with a delayed signal transition (220), the predefined delay defining a first data value. Consequently, the method of the present invention provides a data encoding technique for data communication over a bus that requires less switching activity than other encoding techniques such as pulse width modulation encoding. The present invention further discloses a data communication device (400), a data reception device (500) and a system (300) including these devices, all implementing various aspects of the aforementioned method.
摘要翻译：公开了用于通过包括第一导体（312）和一组其他导体（314）的数据通信总线（310）传送数据的方法（100）。所述方法（300）包括向所述第一导体（312）提供用于用信号通知第一数据通信时段（T1）的开始的第一信号转变（210）; 以及在相对于提供所述第一信号转变（210）的预定延迟之后提供延迟信号转变（220）的另一导体（314），所述预定义延迟定义第一数据值。因此，本发明的方法提供了一种用于通过总线进行数据通信的数据编码技术，与其他编码技术比如脉冲宽度调制编码相比，该技术需要较少的切换活动。本发明还公开了一种数据通信设备（400），数据接收设备（500）和包括这些设备的系统（300），全部实现上述方法的各个方面。

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