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1. 发明申请

WO2007075759A2 JFET WITH DRAIN AND/OR SOURCE MODIFICATION IMPLANT 审中-公开
标题翻译：具有漏极和/或源修改植入物的JFET
公开(公告)号：WO2007075759A2
公开(公告)日：2007-07-05
申请号：PCT/US2006048559
申请日：2006-12-18
申请人： ANALOG DEVICES INC , WILSON CRAIG , BOWERS DEREK , CESTRA GREGORY K
发明人： WILSON CRAIG , BOWERS DEREK , CESTRA GREGORY K
CPC分类号： H01L29/808 , H01L29/0843
摘要： The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e- field. The JFET' s gate layer is preferably sized to have a width which provides respective gaps between the gate, layer' s lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.
摘要翻译：本发明提供一种在制造期间接收附加注入的JFET，其将其漏极区域朝其源极区域和/或其源极区域延伸至其漏极区域。对于给定的漏极和/或源极电压，注入减少了否则在漏极/沟道（和/或源极/沟道）结处出现的电场的幅度，从而降低了栅极电流的严重性以及相关的击穿问题与电子领域。 JFET的栅极层的尺寸优选地具有这样的宽度，其为每个注入在栅极层的横向边界和漏极和/或源极区域之间提供相应的间隙，其中每个注入被注入到相应的间隙中。

2. 发明申请

WO2007075759A3 JFET WITH DRAIN AND/OR SOURCE MODIFICATION IMPLANT 审中-公开
公开(公告)号：WO2007075759A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/048559
申请日：2006-12-18
申请人： ANALOG DEVICES, INC. , WILSON, Craig , BOWERS, Derek , CESTRA, Gregory, K.
发明人： WILSON, Craig , BOWERS, Derek , CESTRA, Gregory, K.
IPC分类号： H01L29/808 , H01L29/08
摘要： The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e- field. The JFET’ s gate layer is preferably sized to have a width which provides respective gaps between the gate, layer' s lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

3. 发明申请

WO2013138223A1 DYNAMIC IMPROVEMENT IN RMS TO DC CONVERTERS 审中-公开
标题翻译：直流转换器的动态改进
公开(公告)号：WO2013138223A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/030142
申请日：2013-03-11
申请人： ANALOG DEVICES, INC. , BOWERS, Derek , COUNTS, Lewis , STALEY, James G.
发明人： BOWERS, Derek , COUNTS, Lewis , STALEY, James G.
IPC分类号： G01R19/02
CPC分类号： G01R19/02 , G01R19/22
摘要： A circuit for providing a DC output equal to the RMS value of a time-varying input signal, the circuit including: (i) an RMS-to-DC converter for producing the DC output and (ii) a high-order low-pass filter comprising at least first and second low-pass filters connected in series to cooperatively reduce at least one of ripple in the DC output, ripple in an denominator feedback loop, or DC error in the DC output.
摘要翻译：一种用于提供等于时变输入信号的RMS值的DC输出的电路，该电路包括：（i）用于产生DC输出的RMS-DC转换器和（ii）高阶低通包括至少串联连接的第一和第二低通滤波器的滤波器，以协同地减少DC输出中的纹波，分母反馈环路中的纹波或DC输出中的DC误差中的至少一个。

4. 发明申请

WO2010105039A1 THERMAL COMPENSATION OF AN EXPONENTIAL PAIR 审中-公开
标题翻译：外在配对的热补偿
公开(公告)号：WO2010105039A1
公开(公告)日：2010-09-16
申请号：PCT/US2010/026958
申请日：2010-03-11
申请人： ANALOG DEVICES, INC. , MODICA, Eric , BOWERS, Derek
发明人： MODICA, Eric , BOWERS, Derek
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F2200/447 , H03F2203/45588 , H03F2203/45594
摘要： To compensate for changes in temperature, a pair of bipolar transistors is connected to a voltage divider and receives a differential voltage that varies with temperature. The voltage divider includes a set of resistors placed in parallel. The set of resistors has a resistance that changes with temperature. As the resistance changes with temperature, the differential voltage provided by the voltage divider changes in proportion to a change in thermal voltage.
摘要翻译：为了补偿温度变化，一对双极晶体管连接到分压器并接收随温度变化的差分电压。分压器包括一组并联放置的电阻器。该组电阻具有随温度变化的电阻。随着电阻随温度变化，由分压器提供的差分电压与热电压的变化成比例地变化。

5. 发明申请

WO2010027773A1 SETTING THE DC OPERATING CURRENT OF A RAIL-TO-RAIL OUTPUT STAGE OF AN OP-AMP 审中-公开
标题翻译：设置OP-AMP的铁路到轨道输出级的直流工作电流
公开(公告)号：WO2010027773A1
公开(公告)日：2010-03-11
申请号：PCT/US2009/054861
申请日：2009-08-25
申请人： ANALOG DEVICES, INC. , MODICA, Eric , BOWERS, Derek
发明人： MODICA, Eric , BOWERS, Derek
IPC分类号： H03F1/30 , H03F3/45 , H03F3/30 , H03F3/343 , G05F3/26 , G05F3/30
CPC分类号： H03F1/307 , H03F1/302 , H03F1/308 , H03F3/3028 , H03F3/3066 , H03F3/3432 , H03F3/4508 , H03F3/45179 , H03F2200/453 , H03F2200/456 , H03F2200/513 , H03F2203/30061
摘要： In an output stage of an operational amplifier, first(2,Q5) and second(Ql,Q4) transistors each provide a collector current under quiescent conditions to first (12, 14) and second (Il,I3)rrent sources. A resistor (Rl, R3) receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor (Q3,Q6) provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor (Ql, Q4).
摘要翻译：在运算放大器的输出级中，第一（2，Q5）和第二（Q1，Q4）晶体管各自在静态条件下为第一（12,14）和第二（I1，I3）电流源提供集电极电流。电阻器（R1，R3）接收一个集电极电流的一部分并产生响应的电阻器电压。输出晶体管（Q3，Q6）提供具有作为电阻器电压和第二晶体管（Q1，Q4）的基极 - 发射极电压的函数计算的值的静态电流。

6. 发明申请

WO2007133416A1 DUAL OP AMP IC WITH SINGLE LOW NOISE OP AMP CONFIGURATION 审中-公开
标题翻译：具有单个低噪声放大器配置的双OP AMP IC
公开(公告)号：WO2007133416A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/010147
申请日：2007-04-24
申请人： ANALOG DEVICES, INC. , BOWERS, Derek, F.
发明人： BOWERS, Derek, F.
IPC分类号： H03F1/26 , H03F3/21 , H03F3/30 , H03F3/45 , H03F3/60
CPC分类号： H03F3/45192 , H03F1/26 , H03F3/211 , H03F3/3069 , H03F3/3083 , H03F3/4521 , H03F3/45475 , H03F3/602 , H03F2200/372 , H03F2203/45138 , H03F2203/45366 , H03F2203/45371
摘要： A multiple op amp IC with a single low noise op amp configuration comprises at least two op amp circuits (40, 42) fabricated on a common substrate. The IC can be configured such that the multiple op amps (40, 42) are connected in parallel to form a single op amp having output drive and input-referred noise characteristics which are superior to those of the constituent op amps. The IC can be fabricated with, either first or second metallization patterns, with the first pattern providing multiple op amps with separate inputs (INA, INB) and outputs (OUTA, OUTB), and the second pattern interconnecting (44, 46, 48) the amplifiers (40, 42) to form a single op amp. The second pattern also preferably interconnects (50) at least one set of correspondin high impedance nodes (52, 54) to prevent a difference voltage which might otherwise arise between the nodes due to componen mismatches between the multiple op amps (40, 42).
摘要翻译：具有单个低噪声运算放大器配置的多运算放大器IC包括在公共衬底上制造的至少两个运算放大器电路（40,42）。 IC可以被配置成使得多个运算放大器（40,42）并联连接以形成具有优于组成运算放大器的输出驱动和输入参考噪声特性的单个运算放大器。 IC可以用第一或第二金属化图案制造，第一图案提供具有单独输入（INA，INB）和输出（OUTA，OUTB）的多个运算放大器，以及第二图案互连（44,46,48）放大器（40,42）以形成单个运算放大器。第二图案还优选地互连（50）至少一组相应的高阻抗节点（52,54），以防止由于多个运算放大器（40,42）之间的组件不匹配而在节点之间可能出现的差异电压。

7. 发明申请

WO2008073170B1 HIGH RESISTIVITY THIN FILM COMPOSITION AND FABRICATION METHOD 审中-公开
标题翻译：高电阻率薄膜组成及其制备方法
公开(公告)号：WO2008073170B1
公开(公告)日：2008-08-07
申请号：PCT/US2007018995
申请日：2007-08-28
申请人： ANALOG DEVICES INC , LEE MICHAEL , WRIGHT STEVEN , JUDGE PHILIP , WILSON CRAIG , CESTRA GREGORY , BOWERS DEREK
发明人： LEE MICHAEL , WRIGHT STEVEN , JUDGE PHILIP , WILSON CRAIG , CESTRA GREGORY , BOWERS DEREK
IPC分类号： H01C7/06
CPC分类号： H01C7/006 , Y10T29/49082
摘要： A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a p of at least 0.02 O-cm (typically 0.02-1.0 O-cm), and a TCR of less than ±1000 ppm/°C (typically less than ±300 ppm/°C). A sheet resistance of at least 20 kO/O may also be obtained. The resulting thin film is preferably at least 200 A (20nm) thick, to reduce surface scattering conduction currents.
摘要翻译：薄膜组合物由硅，绝缘体如氧化铝或二氧化硅，以及至少一种附加材料如铬，镍，硼和/或碳制成。合并这些材料以提供具有至少0.02O-cm（通常0.02-1.0O-cm）的p值和小于±1000ppm /℃（通常小于±300ppm /℃）的TCR的薄膜）。还可以获得至少20kO / O的薄层电阻。所得到的薄膜优选至少200（20nm）厚，以减少表面散射传导电流。

8. 发明申请

WO2008073170A1 HIGH RESISTIVITY THIN FILM COMPOSITION AND FABRICATION METHOD 审中-公开
标题翻译：高电阻薄膜组合物和制造方法
公开(公告)号：WO2008073170A1
公开(公告)日：2008-06-19
申请号：PCT/US2007/018995
申请日：2007-08-28
申请人： ANALOG DEVICES, INC. , LEE, Michael , WRIGHT, Steven , JUDGE, Philip , WILSON, Craig , CESTRA, Gregory , BOWERS, Derek
发明人： LEE, Michael , WRIGHT, Steven , JUDGE, Philip , WILSON, Craig , CESTRA, Gregory , BOWERS, Derek
IPC分类号： H01C7/06
CPC分类号： H01C7/006 , Y10T29/49082
摘要： A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a p of at least 0.02 Ω-cm (typically 0.02-1.0 Ω-cm), and a TCR of less than ±1000 ppm/°C (typically less than ±300 ppm/°C). A sheet resistance of at least 20 kΩ/O may also be obtained. The resulting thin film is preferably at least 200 A (20nm) thick, to reduce surface scattering conduction currents.
摘要翻译：薄膜组合物由硅，诸如氧化铝或二氧化硅的绝缘体和至少一种另外的材料如铬，镍，硼和/或碳制成。将这些材料组合以提供具有至少0.02O-cm（通常为0.02-1.0O-cm）和小于±1000ppm /℃（通常小于±300ppm /℃）的TCR的薄膜）。也可以获得至少20kO / O的薄层电阻。所得薄膜优选为至少200A（20nm）厚，以减少表面散射传导电流。

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