会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • POWER AMPLIFIER
    • 功率放大器
    • WO02050999A1
    • 2002-06-27
    • PCT/IB2001/002200
    • 2001-11-14
    • H03F1/30H03F3/30H03F1/32
    • H03F1/307H03F3/3076
    • The invention relates to devices to amplify electric signals and more particularly, to power amplifiers. The object of the invention is reduction of distortions and the output resistance in power amplifiers in the wide operating frequency. The object is achieved by so in this power amplifier comprising input and output stages, enveloped with the total negative feedback, in addition the local active negative feedback is lead, that lets to stabilize hard the bias voltage of the output stage of a power amplifier, that cases to reduction of distortions and the output resistance in the wide operating frequency.
    • 本发明涉及用于放大电信号的装置,更具体地涉及功率放大器。 本发明的目的是在宽工作频率下减少功率放大器的失真和输出电阻。 该目的通过这样的功率放大器来实现,该功率放大器包括具有总负反馈的输入和输出级,另外局部有源负反馈是导通的,这使得稳定功率放大器的输出级的偏置电压, 在宽工作频率下减少失真和输出电阻的情况。
    • 3. 发明申请
    • AMPLIFIER SUITABLE FOR LOW SUPPLY VOLTAGE OPERATION
    • 适用于低电压运算的放大器
    • WO1983001714A1
    • 1983-05-11
    • PCT/GB1982000321
    • 1982-11-10
    • ADKIN, Francis, Whitmore
    • H03F03/21
    • H03F3/26H03F1/0261H03F1/307
    • An amplifier which is particularly suitable for low supply voltage operation and which is relatively insensitive to power supply voltage variations includes a signal amplifying stage (11) and a control stage (10). The signal amplifying stage (11) includes the output load (13), such as a loudspeaker, in series with a transistor (12) which is controlled by a current mirror circuit (14, 15, 16) in the control stage. The circuit acts by continuously comparing part of the voltage across the output load (13) with a very low reference voltage arising from the difference in the base-emitter voltages of two transistors (14, 15) operating at unequal collector current values. This causes voltage excursion peaks appearing at the junction of the output load (13) and the amplifying transistor (12) to be clamped to a voltage equal to or otherwise related to that at the opposite side of the output load (13).
    • 特别适用于低电源电压并且对电源电压变化相对不敏感的放大器包括信号放大级(11)和控制级(10)。 信号放大级(11)包括与控制级中的电流镜电路(14,15,16)控制的晶体管(12)串联的诸如扬声器的输出负载(13)。 该电路通过将输出负载(13)两端的电压的一部分连续地与由两个以不相等集电极电流值工作的晶体管(14,15)的基极 - 发射极电压的差产生的非常低的参考电压而起作用。 这导致出现在输出负载(13)和放大晶体管(12)的结处的电压偏移峰值被钳位到与输出负载(13)的相反侧相同或相关的电压。
    • 6. 发明申请
    • AUDIO FREQUENCY POWER AMPLIFIER
    • 音频功率放大器
    • WO1995011546A1
    • 1995-04-27
    • PCT/RU1993000244
    • 1993-10-21
    • TOVARISCHESTVO S OGRANICHENNOI OTVETSTVENNOSTJU "e;KVARK"e;SERGEEV, Petr Alexeevich
    • TOVARISCHESTVO S OGRANICHENNOI OTVETSTVENNOSTJU "e;KVARK"e;
    • H03F03/26
    • H03F1/307H03F3/3076
    • The proposed amplifier comprises: an input cascade (1) using an operational amplifier (2), the purpose of this being to create a negative feedback connection common to the alternating and direct currents, in the form of a voltage divider. The operational amplifier (2) draws power via the parametric stabilizers using transistors (3, 4). The voltage amplification cascade (22) is designed as a symmetrical circuit using two transistors (23, 24) forming a circuit with a common base, and is provided with a circuit which creates a potential at the bases of these transistors (23, 24) and includes two groups of diodes (26, 27 and 28, 29) connected in series, the groups being connected via a resistor (30). The current amplification unit (31) is designed as a symmetrical circuit and comprises cascades using transistors (32, 33, 34, 35, 36, 37), connected to a common collector. The output cascade of the unit (31) comprises two resistors (38, 39) connected in series, each of which is connected to the unit's transistors (36, 37). In addition, the unit (31) comprises a thermal stabilizer (43) using transistors (44, 45) of differing structures, while the power amplifier contains a negative feedback circuit common to the direct and alternating currents.
    • 所提出的放大器包括:使用运算放大器(2)的输入级联(1),其目的是以分压器的形式产生对交流和直流电流共同的负反馈连接。 运算放大器(2)通过使用晶体管(3,4)的参数稳定器来吸收功率。 电压放大级联(22)被设计为使用形成具有公共基极的电路的两个晶体管(23,24)的对称电路,并且设置有在这些晶体管(23,24)的基极处产生电位的电路, 并且包括串联连接的两组二极管(26,27和28,29),所述组通过电阻器(30)连接。 电流放大单元(31)被设计为对称电路,并且包括连接到公共集电极的晶体管(32,33,34,35,36,37)的级联。 单元(31)的输出级联包括串联连接的两个电阻器(38,39),每个电阻器连接到单元的晶体管(36,37)。 此外,单元(31)包括使用不同结构的晶体管(44,45)的热稳定器(43),而功率放大器包含与直流和交流电流相同的负反馈电路。
    • 9. 发明申请
    • DIFFERENTIAL OUTPUT STAGE OF AN AMPLIFICATION DEVICE, FOR DRIVING A LOAD
    • 用于驱动负载的放大器件的差分输出级
    • WO2014114632A1
    • 2014-07-31
    • PCT/EP2014/051111
    • 2014-01-21
    • ST-ERICSSON SA
    • COONFALONIERI, PierangeloGUANZIROLI, FedericoNICOLLINI, Germano
    • H03F3/217H03F3/30H03F1/32H03F1/30
    • H03F1/0205H03F1/307H03F1/3205H03F3/183H03F3/211H03F3/217H03F3/2171H03F3/2173H03F3/2178H03F3/3059H03F3/3064H03F3/45179H03F2200/03H03F2200/351H03F2203/21142
    • Differential output stage (200) of an amplification device, for driving a load, comprises a first (201) and a second (202) differential output stage portion. The first differential output stage portion (201) comprises: a first (M1PSW) and a second (M1NSW) output circuit; a first driving circuit (210) comprising a first biasing circuit (M2P, M3N, M4N, R11, I11); a second driving circuit (220) comprising a second biasing circuit (I41, R41, M4P, M3P, M2N). The first differential output stage portion (201) comprises: a third output circuit (M2PSW) connected between a first node (N1) of said first biasing circuit (M2P, M3N, M4N, R11, I11 ) and a first differential output terminal (01), having a third driving terminal (DT3) connected to a first driving terminal (DT1); a fourth output circuit (M2NSW) connected between a first node (N4) of the second biasing circuit (I41, R41, M4P, M3P, M2N) and the first differential output terminal (01), having a fourth driving terminal (DT4) connected to a second driving terminal (DT2).
    • 用于驱动负载的放大装置的差分输出级(200)包括第一(201)和第二(202)差分输出级部分。 第一差分输出级部分(201)包括:第一(M1PSW)和第二(M1NSW)输出电路; 第一驱动电路(210),包括第一偏置电路(M2P,M3N,M4N,R11,I11); 包括第二偏置电路(I41,R41,M4P,M3P,M2N)的第二驱动电路(220)。 第一差分输出级部分(201)包括:连接在所述第一偏置电路(M2P,M3N,M4N,R11,I11)的第一节点(N1)和第一差分输出端子(01)之间的第三输出电路(M2PSW) ),具有连接到第一驱动端子(DT1)的第三驱动端子(DT3); 连接在第二偏置电路(I41,R41,M4P,M3P,M2N)的第一节点(N4)和第一差分输出端子(01)之间的第四输出电路(M2NSW),具有连接的第四驱动端子(DT4) 到第二驱动终端(DT2)。
    • 10. 发明申请
    • CIRCUIT FOR PRECISE SENSING AND REGULATION OF QUIESCENT DC CURRENT IN TRANSISTOR POWER AMPLIFIERS
    • 晶体管功率放大器精密感应直流电流精度检测电路
    • WO00011779A1
    • 2000-03-02
    • PCT/PL1998/000033
    • 1998-08-19
    • H03F1/30H03F1/32
    • H03F1/3217H03F1/307
    • Means and the circuit for extraction of quiescent current from final stages of transistor power amplifiers enabling the sensing and feedback-controlled regulation of that current. In the means, from the voltage UA across the first current sensing resistor RA introduced in series with high current path of first power transistor (or a first substitution set of power transistors) TA conducting the current within first of two half-periods of the sinusoidal output signal or being a harmonic of that signal, and from the voltage UB across the second sensing resistor RB introduced in series with high current path of second power transistor (or a second substitution set of power transistors) TB conducting the current within second half period of the said output signal one creates the sum signal (UA+UB) and the difference signal (UA-UB). From the sum signal (UA+UB) an absolute value |UA+UB| is then derived which is then added to- or subtracted from the above difference signal dependently on the sign of the signal UA across the resistor RA. When the signal UA is positive the proper operation is summation. In contrary when the signal UA is negative one should perform subtraction. As the result one obtains the signal Upp which is proportional to the DC offset of quiescent current flowing through the both high power output transistors TA and TB or through their multi-elemental substitutions. The circuit consists of two current sensing resistors RA and RB introduced in series into high current paths of the respective power output transistors which form the final stage of power amplifier. Each of these resistors is connected to the input of adder 1 which gives (UA+UB) signal as the sum of voltages across RA and RB. Each current sensing resistors RA and RB is connected to the input of second adder 2 which gives the (UA-UB) signal as the difference between the voltages across RA and RB. Output of the first adder 1 is connected via the absolute module function circuit with the input of the third adder 3 whose second input is connected with the output of the second adder 2. At the output of the third adder 3 one obtains signal Upp which is proportional to the offset DC quiescent current of power amplifier.
    • 用于从晶体管功率放大器的最后阶段提取静态电流的方法和电路,使得能够感测和反馈控制该电流的调节。 在这种方式中,从跨过与第一功率晶体管(或第一替代的功率晶体管的替代集合)的高电流路径串联引入的第一电流感测电阻器RA的电压UA在正弦曲线的两个半周期的第一个之前 输出信号或是该信号的谐波,以及从与第二功率晶体管(或功率晶体管的第二替代集合)的高电流路径串联引入的第二感测电阻器RB的电压UB,在第二半周期内导通电流 所述输出信号之一产生和信号(UA + UB)和差分信号(UA-UB)。 从和信号(UA + UB)的绝对值| UA + UB | 然后导出,然后根据上述信号UA在电阻器RA上的符号相加或减去上述差分信号。 当信号UA为正时,正确的操作是求和。 相反,当信号UA为负时,应进行减法。 结果,获得与流过两个高功率输出晶体管TA和TB的静态电流的直流偏移成正比的信号Upp,或通过它们的多元素取代。 该电路由两个电流感测电阻器RA和RB串联引入形成功率放大器最终级的各个功率输出晶体管的高电流通路。 这些电阻器中的每一个连接到加法器1的输入端,其将(UA + UB)信号作为跨越RA和RB的电压之和。 每个电流感测电阻器RA和RB连接到第二加法器2的输入端,该输入端给出(UA-UB)信号作为RA和RB之间的电压之间的差。 第一加法器1的输出经由绝对模块功能电路与第二加法器3的输入连接,第三加法器3的第二输入与第二加法器2的输出相连。在第三加法器3的输出端,获得信号Upp, 与功率放大器的偏移DC静态电流成正比。