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1. 发明申请

WO2008073170B1 HIGH RESISTIVITY THIN FILM COMPOSITION AND FABRICATION METHOD 审中-公开
标题翻译：高电阻率薄膜组成及其制备方法
公开(公告)号：WO2008073170B1
公开(公告)日：2008-08-07
申请号：PCT/US2007018995
申请日：2007-08-28
申请人： ANALOG DEVICES INC , LEE MICHAEL , WRIGHT STEVEN , JUDGE PHILIP , WILSON CRAIG , CESTRA GREGORY , BOWERS DEREK
发明人： LEE MICHAEL , WRIGHT STEVEN , JUDGE PHILIP , WILSON CRAIG , CESTRA GREGORY , BOWERS DEREK
IPC分类号： H01C7/06
CPC分类号： H01C7/006 , Y10T29/49082
摘要： A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a p of at least 0.02 O-cm (typically 0.02-1.0 O-cm), and a TCR of less than ±1000 ppm/°C (typically less than ±300 ppm/°C). A sheet resistance of at least 20 kO/O may also be obtained. The resulting thin film is preferably at least 200 A (20nm) thick, to reduce surface scattering conduction currents.
摘要翻译：薄膜组合物由硅，绝缘体如氧化铝或二氧化硅，以及至少一种附加材料如铬，镍，硼和/或碳制成。合并这些材料以提供具有至少0.02O-cm（通常0.02-1.0O-cm）的p值和小于±1000ppm /℃（通常小于±300ppm /℃）的TCR的薄膜）。还可以获得至少20kO / O的薄层电阻。所得到的薄膜优选至少200（20nm）厚，以减少表面散射传导电流。

2. 发明申请

WO2007075759A2 JFET WITH DRAIN AND/OR SOURCE MODIFICATION IMPLANT 审中-公开
标题翻译：具有漏极和/或源修改植入物的JFET
公开(公告)号：WO2007075759A2
公开(公告)日：2007-07-05
申请号：PCT/US2006048559
申请日：2006-12-18
申请人： ANALOG DEVICES INC , WILSON CRAIG , BOWERS DEREK , CESTRA GREGORY K
发明人： WILSON CRAIG , BOWERS DEREK , CESTRA GREGORY K
CPC分类号： H01L29/808 , H01L29/0843
摘要： The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e- field. The JFET' s gate layer is preferably sized to have a width which provides respective gaps between the gate, layer' s lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.
摘要翻译：本发明提供一种在制造期间接收附加注入的JFET，其将其漏极区域朝其源极区域和/或其源极区域延伸至其漏极区域。对于给定的漏极和/或源极电压，注入减少了否则在漏极/沟道（和/或源极/沟道）结处出现的电场的幅度，从而降低了栅极电流的严重性以及相关的击穿问题与电子领域。 JFET的栅极层的尺寸优选地具有这样的宽度，其为每个注入在栅极层的横向边界和漏极和/或源极区域之间提供相应的间隙，其中每个注入被注入到相应的间隙中。

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