专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017040172A1 METHOD AND APPARATUS FOR MITIGATING PARASITIC COUPLING IN A PACKAGED INTEGRATED CIRCUIT 审中-公开
标题翻译：封装集成电路中缓和耦合的方法和装置
公开(公告)号：WO2017040172A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/048568
申请日：2016-08-25
申请人： ANOKIWAVE, INC.
发明人： JAIN, Vipul , KINAYMAN, Noyan , ESMALI, Amir , MENON, Gaurav , JAIN, Nitin
IPC分类号： H01L21/48 , H01L23/552 , H01L23/495 , H01L23/66
CPC分类号： H01L21/481 , H01L21/565 , H01L23/3121 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/42 , H01L24/46 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6616 , H01L2223/6688 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0557 , H01L2224/0603 , H01L2224/0612 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49111 , H01L2224/49112 , H01L2224/49113 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/32245 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2924/00
摘要： A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.
摘要翻译：封装的IC具有带芯片，信号引线和接地引线的封装。封装的IC还具有固定到封装的裸片，其具有接地焊盘和信号焊盘。信号焊盘电连接到信号引线，并且接地焊盘电连接到管芯焊盘和接地引线。

2. 发明申请

WO2019190595A2 METHOD AND APPARATUS FOR HEAT SINKING HIGH FREQUENCY IC WITH ABSORBING MATERIAL 审中-公开
公开(公告)号：WO2019190595A2
公开(公告)日：2019-10-03
申请号：PCT/US2018/054730
申请日：2018-10-05
申请人： ANOKIWAVE, INC.
发明人： MENON, Gaurav , COMEAU, Jonathan, P. , JAIN, Nitin
IPC分类号： H01L23/66
摘要： A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/ or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

3. 发明申请

WO2018044797A1 PHASED ARRAY CONTROL CIRCUIT 审中-公开
标题翻译：相控阵控制电路
公开(公告)号：WO2018044797A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/048913
申请日：2017-08-28
申请人： ANOKIWAVE, INC.
发明人： MADSEN, Kristian, N. , ALLEN, Wade, C. , COMEAU, Jonathan, P. , MCMORROW, Robert, J. , CORMAN, David, W. , JAIN, Nitim , GRESHAM, Robert, Ian , MENON, Gaurav , JAIN, Vipul
IPC分类号： H01Q3/24 , H01Q3/26
摘要： In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
摘要翻译：在某些示例性实施例中，寄存器组被用于允许相控阵列系统中的快速波束切换（FBS）。具体而言，每个波束成形信道与包含M个寄存器组的寄存器组相关联，用于配置波束成形信道的增益/幅度和相位参数等。所有波束形成通道的寄存器组可以被预先编程，然后快速波束切换电路允许阵列上的所有波束形成通道被切换到基本上同时使用来自其相应寄存器组的相同寄存器组，相控阵系统可在各种光束模式和方向之间快速切换。附加地或可替代地，有源功率控制电路可以用于控制提供给一个或多个单独波束成形信道或由一个或多个单独波束成形信道消耗的电功率量，以便减少阵列的DC功率消耗和/或选择性地改变有效方向性数组。

4. 发明申请

WO2018017445A1 PHASED ARRAY BURST SAMPLER 审中-公开
标题翻译：相控阵雷达采样器
公开(公告)号：WO2018017445A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/042311
申请日：2017-07-17
申请人： ANOKIWAVE, INC.
发明人： ALLEN, Wade, C. , MCMORROW, Robert, J. , CORMAN, David, W.
IPC分类号： H04B7/005 , H01Q21/00
摘要： An active electronic steered antenna (AESA) circuit monitors bursts of a phased array that has a plurality of signal chains. Each signal chain therefore has a burst output for transmitting at least one burst. To monitor bursts, the AESA circuit has an input that is operably couplable with the burst output of at least one signal chain of the phased array. The input is configured to receive one or more bursts transmitted by the burst output(s) of the at least one signal chain. The AESA circuit also has a sample circuit operably coupled with the input and configured to sample the one or more bursts to produce one or more corresponding samples, and memory operably coupled with the sample circuit. The memory receives and stores the one or more samples. To provide access to the samples, the AESA circuit also has a memory interface.
摘要翻译：有源电子控制天线（AESA）电路监视具有多个信号链的相控阵列的突发。因此每个信号链具有用于传输至少一个突发的突发输出。为了监视突发，AESA电路具有可操作地与相控阵列的至少一个信号链的突发输出耦合的输入。输入被配置为接收由至少一个信号链的突发输出发送的一个或多个突发。 AESA电路还具有与输入端可操作地耦合并且被配置为对一个或多个突发进行采样以产生一个或多个对应采样的采样电路，以及可操作地与采样电路耦合的存储器。存储器接收并存储一个或多个样本。为了提供对样本的访问，AESA电路还具有存储器接口。

5. 发明申请

WO2021026398A2 SPUR MITIGATION IN A HETERODYNE UPCONVERSION SYSTEM 审中-公开
公开(公告)号：WO2021026398A2
公开(公告)日：2021-02-11
申请号：PCT/US2020/045292
申请日：2020-08-06
申请人： ANOKIWAVE, INC.
发明人： GRESHAM, Robert, Ian , RAVID, Shmuel , MADSEN, Kristian, N. , KIJSANAYOTIN, Tissana, T.
IPC分类号： H03G1/00 , H04B1/406
摘要： Exemplary embodiments dynamically select the LO frequency and mixer mode (i.e., low-side LO injection or high-side LO injection) for upconversion based on the desired RF output frequency in order to mitigate the effects of spurious and LO leakage signals that could violate radiation emission limits, e.g., in the case where the IF signal frequency is smaller than the RF operating band. By dynamically switching the LO frequency and mixer mode as a function of the requested operating RF channel, low-level emissions and spurious signal compliance with restricted bands can be achieved.

6. 发明申请

WO2019071210A1 THERMAL MANAGEMENT METHOD AND APPARATUS FOR HIGH FREQUENCY IC WITH APERTURED HEAT SINK 审中-公开
公开(公告)号：WO2019071210A1
公开(公告)日：2019-04-11
申请号：PCT/US2018/054727
申请日：2018-10-05
申请人： ANOKIWAVE, INC.
发明人： MENON, Gaurav , COMEAU, Jonathan P. , STREET, Andrew , MITCHELL, Scott , MCMORROW, Robert, J. , JONES, Christopher
IPC分类号： H01L23/00 , H01L23/367 , H01L23/495
摘要： An integrated circuit system has a die with first and second sides, and contains high frequency circuitry operating at mm-wave frequencies. The system also has a plurality of interfaces (on the first side) in electrical communication with the high frequency circuitry, and a heat sink having a bottom surface with a first region and an aperture region. The first region is in physical and conductive contact with the die, while the aperture region forms a concavity with an inner concave surface that is spaced from the die.

7. 发明申请

WO2018118169A1 PHASED ARRAY WITH BEAMFORMING INTEGRATED CIRCUIT HAVING TWO SIGNAL CHAINS 审中-公开
公开(公告)号：WO2018118169A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/053356
申请日：2017-09-26
申请人： ANOKIWAVE, INC.
发明人： MCMORROW, Robert, J. , JAIN, Vipul , ALLEN, Wade, C. , CORMAN, David, W. , GRESHAM, Robert, Ian , MADSEN, Kristian, N. , JAIN, Nitin
IPC分类号： H01Q3/00 , H01Q3/26 , H01Q25/00
摘要： A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

8. 发明申请

WO2021141667A2 INTEGRATED CIRCUIT AND SYSTEMS WITH TRACKING 审中-公开
公开(公告)号：WO2021141667A2
公开(公告)日：2021-07-15
申请号：PCT/US2020/060502
申请日：2020-11-13
申请人： ANOKIWAVE, INC.
发明人： FARSI, Saeed , JAIN, Vipul , JACOBS, Zarion , COMEAU, Jonathan, P. , RAVID, Shmuel , COSKUN, Hakan
IPC分类号： H01Q21/06 , H01Q23/00 , H01Q21/10 , H01Q21/22 , H01Q21/0006 , H01Q21/065 , H01Q3/2605 , H01Q3/267 , H01Q3/28 , H01Q3/385 , H04B17/102
摘要： A beamforming IC operates in a transmit mode or a receive mode to respectively transmit and receive signals at different times. To that end, the beamforming IC has an element interface, a transmit branch configured to produce an output transmit signal through the element interface when in the transmit mode, and a receive branch configured to receive an input signal through the element interface when in the receive mode. The beamforming circuit also has a sampling circuit with an electrical coupling with the transmit branch. The sampling circuit is configured to sample the output transmit signal with the electrical coupling to produce a sample signal. The sampling circuit also is configured to direct the sample signal through the receive branch, which is configured to modify the phase of the sample signal to produce a modified sample signal. This modified sample signal can be used to manage the IC transmission.

9. 发明申请

WO2021030140A1 BEAMFORMING INTEGRATED CIRCUIT HAVING RF SIGNAL PORTS USING A GROUND-SIGNAL TRANSITION FOR HIGH ISOLATION IN A PHASED ANTENNA ARRAY SYSTEM AND RELATED METHODS 审中-公开
公开(公告)号：WO2021030140A1
公开(公告)日：2021-02-18
申请号：PCT/US2020/045182
申请日：2020-08-06
申请人： ANOKIWAVE, INC.
发明人： GREENE, Kevin , IBRAHIM, Amir , JAIN, Vipul
IPC分类号： H04B7/06 , H01Q21/06
摘要： A phased antenna array system is provided that includes a beamforming integrated circuit and beamforming elements in communication with the integrated circuit disposed on a substrate. The beamforming integrated circuit includes multiple radio frequency (RE) signal ports. One or more of the RE signal ports includes an RE signal pad disposed between an edge of the integrated circuit and an internal RE ground pad. The RE signal pad and the internal RE ground pad of the RE signal port are oriented perpendicular with respect to the edge of the integrated circuit. Specifically, the RE signal pad has a first side disposed on or adjacent to the edge of the integrated circuit and an opposing second side that is adjacent to the internal RE ground pad. A method of controlling the phased antenna array system is also provided.

10. 发明申请

WO2019195684A1 PHASED ARRAY ARCHITECTURE WITH DISTRIBUTED TEMPERATURE COMPENSATION AND INTEGRATED UP/DOWN CONVERSION 审中-公开
公开(公告)号：WO2019195684A1
公开(公告)日：2019-10-10
申请号：PCT/US2019/025997
申请日：2019-04-05
申请人： ANOKIWAVE, INC.
发明人： MADSEN, Kristian N. , MCMORROW, Robert J. , CORMAN, David W. , JAIN, Nitin , GRESHAM, Robert Ian , MENON, Gaurav , JAIN, Vipul , COMEAU, Jonathan P. , RAVID, Shmuel
IPC分类号： H03H7/54 , H01Q3/26 , H04B7/00
摘要： A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式