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71. 发明申请

WO2015099899A1 METHODS OF FORMING A MAGNETIC RANDOM ACCESS MEMORY ETCH SPACER AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成磁性随机存取存储器间隔器的方法及其形成的结构
公开(公告)号：WO2015099899A1
公开(公告)日：2015-07-02
申请号：PCT/US2014/065984
申请日：2014-11-17
申请人： INTEL CORPORATION
发明人： LAMBORN, Daniel R. , GOLONZKA, Oleg , WIEGAND, Christopher
IPC分类号： H01L43/10 , H01L43/12
CPC分类号： H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Methods of forming a memory device structure are described. Those methods may include forming a non-conductive spacer material on a top electrode of a magnetic tunnel junction structure, and then forming a highly selective material on the non-conductive spacer material of the magnetic tunnel junction prior to etching a bottom electrode of the magnetic tunnel junction.
摘要翻译：描述形成存储器件结构的方法。这些方法可以包括在磁性隧道结结构的顶部电极上形成非导电间隔物材料，然后在蚀刻磁性体的底部电极之前在磁性隧道结的非导电间隔物材料上形成高选择性材料隧道交界处。

72. 发明申请

WO2015094488A1 SELF-ALIGNED VIA PATTERNING WITH MULTI-COLORED PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
标题翻译：自动对准通过多行彩色胶片的背面（BEOL）互连
公开(公告)号：WO2015094488A1
公开(公告)日：2015-06-25
申请号：PCT/US2014/063128
申请日：2014-10-30
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , MYERS, Alan M. , SINGH, Kanwal J.
IPC分类号： H01L21/768 , H01L21/60
CPC分类号： H01L21/0338 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/31144 , H01L21/76801 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure. Dielectric lines of the second grating overlap and contact, but are distinct from, dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.
摘要翻译：描述了通过用于后端（BEOL）互连的多色photobuckets图案化的自对准。在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。互连结构的第二层设置在互连结构的第一层之上。第二光栅的介电线与第一光栅的介质线重叠和接触，但不同。第一和第二电介质区域设置在第一光栅的金属线和第二光栅的金属线之间，并且在与第一光栅的介质线的上部和第二栅的介电线的下部相同的平面中光栅。第一电介质区域由第一交联光可光化材料组成，第二电介质区域由第二不同的交联光可光化材料组成。

73. 发明申请

WO2015094470A1 APPARATUS FOR REDUCING PERIODIC JITTER IN A RING OSCILLATOR 审中-公开
标题翻译：减轻环形振荡器周期性抖动的装置
公开(公告)号：WO2015094470A1
公开(公告)日：2015-06-25
申请号：PCT/US2014/061384
申请日：2014-10-20
申请人： INTEL CORPORATION
发明人： BICHAN, Michael E. , WANG, Robert H.
IPC分类号： H03K3/356 , H03L7/099
CPC分类号： H03K3/0315 , H03K3/013
摘要： Described is an apparatus which comprises: a first power supply node to provide power supply current; a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply current provided to the ring oscillator; and a second power supply node; a circuit, coupled to the second power supply node, to replicate time-average (e.g., DC) behavior of the ring oscillator; and a feedback mechanism having inputs coupled to the first and second power supply nodes, and an output to control current in the circuit.
摘要翻译：描述了一种装置，包括：提供电源电流的第一电源节点; 环形振荡器，耦合到第一电源节点，以根据提供给环形振荡器的电源电流的变化产生振荡输出; 和第二电源节点; 耦合到所述第二电源节点的电路，以复制所述环形振荡器的时间平均（例如DC）行为; 以及具有耦合到第一和第二电源节点的输入的反馈机构，以及控制电路中的电流的输出。

74. 发明申请

WO2015088708A2 FLEXIBLE MICROMACHINED TRANSDUCER DEVICE AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：柔性微型传感器装置及其制造方法
公开(公告)号：WO2015088708A2
公开(公告)日：2015-06-18
申请号：PCT/US2014/065964
申请日：2014-11-17
申请人： FUJIFILM DIMATIX, INC.
发明人： LATEV, Dimitre , HAJATI, Arman , IMAI, Darren Todd , TRAN, Ut
IPC分类号： B06B1/02 , B32B37/24 , B06B1/06
CPC分类号： H01L41/042 , B06B1/0622 , B32B37/12 , B32B37/185 , B32B2457/00 , H01L41/0475 , H01L41/098 , H01L41/29 , Y10T156/10
摘要： Techniques and structures for providing flexibility of a micromachined transducer array. In an embodiment, a transducer array includes a plurality of transducer elements each comprising a piezoelectric element and one or more electrodes disposed in or on a support layer. The support layer is bonded to a flexible layer including a polymer material, wherein flexibility of the transducer array results in part from a total thickness of a flexible layer. In another embodiment, flexibility of the transducer array results in part from one or more flexural structures formed therein.
摘要翻译：提供微机械传感器阵列的灵活性的技术和结构。在一个实施例中，换能器阵列包括多个换能器元件，每个换能器元件包括压电元件和设置在支撑层中或支撑层上的一个或多个电极。支撑层结合到包括聚合物材料的柔性层，其中换能器阵列的灵活性部分地来自柔性层的总厚度。在另一个实施例中，换能器阵列的灵活性部分地由其中形成的一个或多个弯曲结构导致。

75. 发明申请

WO2015088642A1 HIGHLY SELECTIVE COATED-ELECTRODE NANOGAP TRANSDUCERS FOR THE DETECTION OF REDOX MOLOCULES 审中-公开
标题翻译：用于检测红葡萄酒的高选择性涂层电极纳米转印膜
公开(公告)号：WO2015088642A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/060474
申请日：2014-10-14
申请人： INTEL CORPORATION
发明人： TAYEBI, Noureddine , SU, Xing , LI, Handong
IPC分类号： G01N27/30 , G01N33/48
CPC分类号： G01N27/3278 , C23C16/00
摘要： Highly selective coated-electrode nanogap transducers for the detection of redox molecules are described. In an example, an analyte detection system includes one or more transducer electrodes having a surface for analyte detection. The surface includes a coating to inhibit direct contact of analyte with the surface of the one or more transducer electrodes.
摘要翻译：描述了用于检测氧化还原分子的高选择性涂层电极纳米胶片转换器。在一个示例中，分析物检测系统包括具有用于分析物检测的表面的一个或多个换能器电极。表面包括抑制分析物与一个或多个换能器电极的表面的直接接触的涂层。

76. 发明申请

WO2015047700A1 METHOD AND APPARATUS FOR CACHE OCCUPANCY DETERMINATION AND INSTRUCTION SCHEDULING 审中-公开
标题翻译：高速缓存的确定方法和装置及指导性调度
公开(公告)号：WO2015047700A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/054491
申请日：2014-09-08
申请人： INTEL CORPORATION
发明人： ZAKS, Ayal , VALENTINE, Robert , NARKIS, Arie
IPC分类号： G06F9/46
CPC分类号： G06F12/0811 , G06F9/30047 , G06F9/383 , G06F12/08 , G06F12/084 , G06F12/0842 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/0888 , G06F12/0897 , G06F2212/1016 , G06F2212/502
摘要： An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on the determination. For example, one embodiment of a processor comprises: a hierarchy of cache levels for caching data including at least a level 1 (L1) cache; cache occupancy determination logic to determine whether data associated with one or more subsequent operations is stored in one of the cache levels; and scheduling logic to schedule execution of the subsequent operations based on the determination of whether data associated with the subsequent operations is stored in the cache levels.
摘要翻译：一种用于确定一个或多个操作所需的数据是否存储在高速缓存中的装置和方法，并且基于该确定来调度用于执行的操作。例如，处理器的一个实施例包括：高速缓存级别的层级，用于缓存包括至少第1级（L1）高速缓存的数据; 高速缓存占用确定逻辑，用于确定与一个或多个后续操作相关联的数据是否存储在所述高速缓存级别之一中; 以及调度逻辑，以基于确定与后续操作相关联的数据是否存储在高速缓存级别来调度后续操作的执行。

77. 发明申请

WO2015047267A1 METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES 审中-公开
标题翻译：在NMOS结构中形成分解增强应变的方法
公开(公告)号：WO2015047267A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061859
申请日：2013-09-26
申请人： INTEL CORPORATION , JACKSON, Michael , MURTHY, Anand , GLASS, Glenn , MORARKA, Saurabh , MOHAPATRA, Chandra
发明人： JACKSON, Michael , MURTHY, Anand , GLASS, Glenn , MORARKA, Saurabh , MOHAPATRA, Chandra
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0673 , H01L29/1033 , H01L29/165 , H01L29/32 , H01L29/66568 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
摘要翻译：描述了利用设置在源极/漏极结构中的位错形成应变通道器件的方法。这些方法和结构可以包括在包括硅的器件的源/漏开口中形成薄硅锗材料，其中在硅锗材料中形成多个位错。源/漏材料可以形成在薄硅锗材料上，其中位错在器件的沟道区域中引起拉伸应变。

78. 发明申请

WO2015047264A1 METHODS OF FORMING LOW BAND GAP SOURCE AND DRAIN STRUCTURES IN MICROELECTRONIC DEVICES 审中-公开
标题翻译：在微电子设备中形成低带隙源和漏极结构的方法
公开(公告)号：WO2015047264A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061832
申请日：2013-09-26
申请人： INTEL CORPORATION , RIOS, Rafael , KOTLYAR, Roza , KUHN, Kelin
发明人： RIOS, Rafael , KOTLYAR, Roza , KUHN, Kelin
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02535 , H01L21/28512 , H01L29/0847 , H01L29/165 , H01L29/401 , H01L29/41725 , H01L29/45 , H01L29/66477 , H01L29/66795
摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.
摘要翻译：描述了利用设置在源极/漏极结构中的位错形成应变通道器件的方法。这些方法/结构可以包括在器件的衬底中形成源极/漏极区域，以及在源极/漏极区域中形成合金，其中所述合金包括降低源极/漏极接触点与源极/漏极接触点之间的带隙的材料，漏极区域基本上为零。这里的实施例减小了器件的外部寄生电阻。

79. 发明申请

WO2015047233A1 METHODS OF FORMING BURIED VERTICAL CAPACITORS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成BURIED垂直电容器的方法及其形成的结构
公开(公告)号：WO2015047233A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061538
申请日：2013-09-25
申请人： INTEL CORPORATION , GASKARAN, Rajashree , JUN, Kimin , MORROW, Patrick
发明人： GASKARAN, Rajashree , JUN, Kimin , MORROW, Patrick
IPC分类号： H01L21/20
CPC分类号： H01L27/10832 , H01L21/84 , H01L27/0629 , H01L27/0688 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L28/20 , H01L28/87 , H01L28/91 , H01L29/945
摘要： Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.
摘要翻译：描述了在器件层下形成无源元件的方法。这些方法和结构可以包括在衬底中形成至少一个无源结构，例如电容器和电阻器结构，其中被动结构垂直地设置在衬底内。绝缘体层形成在无源结构的顶表面上，在绝缘体层上形成器件层，并且形成接触件以将布置在器件层中的器件耦合到至少一个被动结构。

80. 发明申请

WO2015026437A1 MULTI-LAYERED THIN FILM PIEZOELECTRIC DEVICES & METHODS OF MAKING THE SAME 审中-公开
标题翻译：多层薄膜压电器件及其制造方法
公开(公告)号：WO2015026437A1
公开(公告)日：2015-02-26
申请号：PCT/US2014/043893
申请日：2014-06-24
申请人： FUJIFILM DIMATIX, INC.
发明人： LI, Youming
IPC分类号： H01L41/083 , H01L41/18
CPC分类号： H01L41/0471 , H01L41/0805 , H01L41/083 , H01L41/0973 , H01L41/098 , H01L41/27
摘要： Multi-layered thin film piezoelectric material stacks and devices incorporating such stacks. In embodiments, an intervening material layer is disposed between two successive piezoelectric material layers in at least a portion of the area of a substrate over which the multi-layered piezoelectric material stack is disposed. The intervening material may serve one or more function within the stack including, but not limited to, inducing an electric field across one or both of the successive piezoelectric material layers, inducing a discontinuity in the microstructure between the two successive piezoelectric materials, modulating a cumulative stress of the piezoelectric material stack, and serving as a basis for varying the strength of an electric field as a function of location over the substrate.
摘要翻译：多层薄膜压电材料堆叠和结合这样的堆叠的装置。在实施例中，中间材料层设置在衬底的至少一部分区域中的两个连续的压电材料层之间，多层压电材料堆叠设置在该区域上。中间材料可以在堆叠内用于一个或多个功能，包括但不限于在一个或两个连续的压电材料层上引起电场，从而引起两个连续的压电材料之间的微结构的不连续性，压电材料堆的应力，并且作为改变作为衬底上位置的函数的电场强度的基础。

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