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71. 发明申请

WO2017003411A1 MULTI-HEIGHT FINFET DEVICE BY SELECTIVE OXIDATION 审中-公开
标题翻译：通过选择性氧化的多高度FINFET器件
公开(公告)号：WO2017003411A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038194
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： KIM, Seiyon , BHIMARASETTI, Gopinath , RIOS, Rafael , KAVALIEROS, Jack T. , GHANI, Tahir , MURTHY, Anand S. , MEHANDRU, Rishabh
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02546 , H01L23/49827 , H01L23/49838 , H01L27/0886 , H01L27/1211 , H01L29/0847 , H01L29/1037 , H01L29/66545 , H01L29/78 , H01L29/785 , H01L29/7851
摘要： A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.
摘要翻译：一种方法，包括在衬底上形成多栅极器件的非平面导电沟道，所述沟道包括从所述衬底的表面处的基底限定的高度尺寸; 修改小于通道的整个部分; 以及在所述沟道上形成栅极堆叠，所述栅极堆叠包括电介质材料和栅电极。一种包括在基板上的非平面多栅极器件的装置，包括包括限定导电部分的高度尺寸的沟道和设置在沟道上的氧化部分和栅极堆叠，栅极堆叠包括电介质材料和栅电极。

72. 发明申请

WO2017003410A1 INTEGRATION METHOD FOR FINFET WITH TIGHTLY CONTROLLED MULTIPLE FIN HEIGHTS 审中-公开
标题翻译：具有精细控制的多个FIN HEIGHTS的FINFET的集成方法
公开(公告)号：WO2017003410A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038193
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： KIM, Seiyon , KAVALIEROS, Jack T. , MURTHY, Anand S. , GLASS, Glenn A. , JAMBUNATHAN, Karthik
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/823431 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.
摘要翻译：一种包括在衬底上形成非平面器件的鳍的方法，所述鳍包括在第一层和第三层之间的第二层; 用介电材料代替第二层; 以及在所述鳍的沟道区上形成栅叠层。一种包括在基板上的第一多重装置的装置，包括在电介质层上包括导电层的鳍片，设置在鳍片的沟道区域中的导电层上的栅极叠层以及形成在鳍片中的源极和漏极，以及所述基板上的第二多重装置包括：散热片，包括由电介质层分离的第一导电层和第二导电层;栅极堆叠，其设置在所述鳍片的沟道区域中的所述第一导电层和所述第二导电层;以及源极以及在翅片中形成的排水口。

73. 发明申请

WO2017003408A1 METHOD TO FORM OHMIC CONTACTS TO SEMICONDUCTORS USING QUANTIZED METALS 审中-公开
标题翻译：使用量化金属形成与半导体的OHMIC接触的方法
公开(公告)号：WO2017003408A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038191
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： CHU-KUNG, Benjamin , LE, Van H. , RIOS, Rafael , DEWEY, Gilbert , CLENDENNING, Scott B. , KAVALIEROS, Jack T.
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/28
CPC分类号： H01L29/45 , H01L21/28556 , H01L21/28568 , H01L21/76802 , H01L21/76883 , H01L23/49827 , H01L23/49838 , H01L29/0847 , H01L29/41783 , H01L29/66568 , H01L29/78
摘要： An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.
摘要翻译：一种包括集成电路装置的装置，其包括至少一种低密度状态金属/半导体材料界面，其中所述至少一种低密度状态金属被量化。一种包括集成电路装置的装置，其包括至少一个低密度状态金属和半导体材料的界面，其中金属在界面处的接触面积被分级。一种包括限制半导体材料的接触面积的方法; 以及在所述接触区域中形成金属接触。

74. 发明申请

WO2017003407A1 GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER 审中-公开
标题翻译：具有GAAS的GE NANO线状晶体管作为绝对层
公开(公告)号：WO2017003407A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038190
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KAVALIEROS, Jack T. , GARDNER, Sanaz K.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6681 , H01L21/0243 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/30612 , H01L27/0924 , H01L29/0673 , H01L29/068 , H01L29/0847 , H01L29/16 , H01L29/20 , H01L29/267 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/7853
摘要： An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
摘要翻译：一种包括三维半导体本体的装置，包括沟道区和设置在沟道区的相对侧的结区，所述三维半导体本体包括多个纳米线，所述多个纳米线包括设置在通过所述接合区域分离的各个平面中的锗材料，第二材料，其中所述第二材料的晶格常数类似于所述锗材料的晶格常数; 以及设置在所述沟道区上的栅极堆叠，所述栅极堆叠包括设置在栅极电介质上的栅电极。一种包括在衬底上的分离平面中形成多个纳米线的方法，所述多个纳米线中的每一个包括锗材料并通过牺牲材料与相邻的纳米线分离; 在指定的沟道区域中的多个纳米线上设置栅极堆叠，所述栅极堆叠包括电介质材料和栅电极。

75. 发明申请

WO2016105437A1 HIGH MOBILITY NANOWIRE FIN CHANNEL ON SILICON SUBSTRATE FORMED USING SACRIFICIAL SUB-FIN 审中-公开
标题翻译：使用SACRIFICIAL SUB-FIN形成的硅基板上的高移动性NANOWIRE FIN通道
公开(公告)号：WO2016105437A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072448
申请日：2014-12-26
申请人： INTEL CORPORATION , DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
发明人： DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
IPC分类号： H01L21/762 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/30604 , H01L21/31111 , H01L21/7605 , H01L21/762 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/122 , H01L29/161 , H01L29/20 , H01L29/66469 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
摘要翻译：集成电路管芯包括用于晶体管（例如，作为MOS器件的沟道的单个材料或堆叠）的沟道材料的四栅极器件纳米线，其通过从沟道材料的下方去除一部分子鳍材料而形成，其中亚翅片材料在长宽比捕集（ART）沟槽中生长。在某些情况下，在形成这样的纳米线时，可以去除通道下的有缺陷的翅片材料或区域。这种去除隔离了翅片通道，去除了翅片缺陷和泄漏路径，并且形成具有四个暴露表面的通道材料的纳米线，栅极材料可以形成在其上。

76. 发明申请

WO2016105436A1 SPIN-ORBIT LOGIC WITH CHARGE INTERCONNECTS AND MAGNETOELECTRIC NODES 审中-公开
标题翻译：具有电荷互连和磁电效应的旋转逻辑
公开(公告)号：WO2016105436A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072447
申请日：2014-12-26
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02
CPC分类号： H01L27/22 , H01L27/228 , H01L43/08 , H03K19/173 , H03K19/18
摘要： An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.
摘要翻译：一种包括旋转电荷转换节点的装置; 以及对自旋转换节点的电荷，其中到自旋电荷转换节点的输入在电荷到自旋转换节点处产生输出。一种包括包括输入节点和输出节点的磁体的装置，所述输入节点包括可操作以在所述磁体中产生磁响应的电容器，所述输出节点包括至少一个自旋电荷转换材料。一种包括从第一磁体注入自旋电流的方法; 将自旋电流转换成可操作以产生与第二磁体的磁电相互作用的充电电流; 以及响应于所述磁电相互作用而改变所述第二磁体的磁化方向。一种包括从磁体的输入节点注入自旋电流的方法; 以及将所述自旋电流转换为所述磁体的输出节点处的充电电流。

77. 发明申请

WO2016048383A1 SUBSTRATE WARPAGE CONTROL USING TEMPER GLASS WITH UNI-DIRECTIONAL HEATING 审中-公开
标题翻译：使用具有单向加热的温度玻璃的基板温度控制
公开(公告)号：WO2016048383A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057921
申请日：2014-09-27
申请人： INTEL CORPORATION
发明人： CHUNG, Chee Key , SHUTO, Takashi
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L21/67092 , H01L21/3247 , H01L21/4846 , H01L21/67098 , H01L21/68721 , H01L21/68785 , H01L23/49811 , H01L23/49816 , H01L2924/0002 , H01L2924/00
摘要： A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a heat source from a single direction; and modifying a shape of the package substrate. An apparatus including a first and second supporting substrates, the first supporting substrate including a two-dimensional area that is 75 percent to 95 percent of the area of the first side of the package substrate and the second supporting substrate including a two-dimensional area that is at least equivalent to the area of a package substrate and each of the first supporting substrate and the second supporting substrate include a body having a cavity therein such that when assembled on opposite sides of a package substrate, each cavity has a volume dimension such that the body of the supporting substrate is not in contact with an area of a package substrate.
摘要翻译：一种包括在第一和第二支撑衬底之间夹紧集成电路封装衬底的方法; 将夹持的封装衬底从单个方向暴露于热源; 以及修改封装衬底的形状。一种包括第一和第二支撑基板的装置，所述第一支撑基板包括二维区域，所述二维区域是所述封装基板的第一侧面积的75％至95％，所述第二支撑基板包括二维区域，所述二维区域至少等同于封装基板的面积，并且第一支撑基板和第二支撑基板中的每一个包括其中具有空腔的主体，使得当在封装基板的相对侧上组装时，每个空腔的体积尺寸使得支撑基板的主体不与封装基板的区域接触。

78. 发明申请

WO2016048379A1 METHOD OF FABRICATING CRYSTALLINE MAGNETIC FILMS FOR PSTTM APPLICATIONS 审中-公开
标题翻译：用于PSTTM应用的晶体磁性薄膜的制备方法
公开(公告)号：WO2016048379A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057879
申请日：2014-09-26
申请人： INTEL CORPORATION , O'BRIEN, Kevin P. , DOYLE, Brian S. , OGUZ, Kaan , CHAU, Robert S. , SURI, Satyarth
发明人： O'BRIEN, Kevin P. , DOYLE, Brian S. , OGUZ, Kaan , CHAU, Robert S. , SURI, Satyarth
IPC分类号： G11C11/16
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/08 , H01L43/10
摘要： A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.
摘要翻译：一种方法，包括在包括类似于电介质材料的晶格的晶格的全结晶牺牲膜或衬底上形成包括固定磁性层和自由磁性层之间的电介质层的器件堆叠; 以及将器件堆叠从牺牲膜转移到器件衬底。一种装置，包括：器件堆叠，其包括在器件衬底上的固定磁性层和自由磁性层之间的介电层，其中固定磁性层和自由磁性层各自具有与牺牲膜或衬底的晶格相符的晶格在转移到器件基板之前形成它们。

79. 发明申请

WO2015191593A1 VIRTUAL NEONATAL ECHOCARDIOGRAPHIC TRAINING SYSTEM 审中-公开
标题翻译：虚拟新生教育培训系统
公开(公告)号：WO2015191593A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/034921
申请日：2015-06-09
申请人： BIJAN, Siassi
发明人： BIJAN, Siassi
IPC分类号： G09B23/28 , G09B23/30
CPC分类号： G09B23/288 , G06F19/00 , G09B23/28 , G09B23/281 , G09B23/285 , G09B23/286 , G09B23/30 , G09B23/34
摘要： A neonatal echocardiography training apparatus including (i) a computer; (ii) a life-sized doll mannequin; (iii) a magnetic tracking system including (a) a control module connected to the computer; (b) a magnetic pulse wave generator positioned behind the mannequin and connected to the control module; (c) a sensor-fitted transducer configured to detect magnetic pulse waves from the generator and connected to the control module; and wherein the control module reads data from the generator and transducer and transmits the data to the computer. A method of displaying continuous video clips obtained from slicing of multiple 4D echocardiographic image volumes and 2D video clips activated from the coordinates of slices of 4D volumes is described. These echocardiographic images are displayed when a trainee positions the transducer on the desired cardiac acoustic window on the mannequin.
摘要翻译：一种新生儿超声心动图训练装置，包括（i）计算机; （ii）一个真人大小的娃娃人体模特; （iii）磁跟踪系统，包括：（a）连接到所述计算机的控制模块; （b）位于人体模型后面并连接到控制模块的磁脉冲波发生器; （c）配备传感器的传感器，其被配置为检测来自所述发生器并连接到所述控制模块的磁脉冲波; 并且其中所述控制模块从所述发生器和换能器读取数据并将所述数据发送到所述计算机。描述从4D卷的切片的坐标激活的多个4D超声心动图像体积和2D视频剪辑的切片获得的连续视频剪辑的显示方法。当受训者将换能器定位在人体模型上所需的心音声窗上时，显示这些超声心动图。

80. 发明申请

WO2015099784A1 BI-AXIAL TENSILE STRAINED GE CHANNEL FOR CMOS 审中-公开
标题翻译：用于CMOS的双向拉伸应变通道
公开(公告)号：WO2015099784A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/078100
申请日：2013-12-27
申请人： INTEL CORPORATION , MAJHI, Prashant , MUKHERJEE, Niloy , PILLARISETTY, Ravi , RACHMADY, Willy , CHAU, Robert, S.
发明人： MAJHI, Prashant , MUKHERJEE, Niloy , PILLARISETTY, Ravi , RACHMADY, Willy , CHAU, Robert, S.
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823807 , H01L29/0649 , H01L29/0673 , H01L29/1054 , H01L29/165 , H01L29/267 , H01L29/42392 , H01L29/78669 , H01L29/78684
摘要： An apparatus comprising a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.
摘要翻译：一种包括具有n沟道金属氧化物半导体场效应晶体管（MOSFET）的互补金属氧化物半导体（CMOS）反相器的装置; 以及p沟道MOSFET，其中n沟道MOSFET中的沟道材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。一种包括形成n沟道金属氧化物半导体场效应晶体管（MOSFET）的方法; 形成p沟道MOSFET; 以及连接n沟道MOSFET和p沟道MOSFET的栅电极和漏极区，其中n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料受到双向拉伸应变。

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