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51. 发明申请

WO00070621A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO00070621A1
公开(公告)日：2000-11-23
申请号：PCT/JP1999/002504
申请日：1999-05-14
IPC分类号： G11C11/406 , G11C11/407
CPC分类号： G11C11/406
摘要： A semiconductor integrated circuit device comprising a memory which includes memory cells and circuit blocks, power supply switching means, and a refresh controller and having first and second operating modes, wherein the refresh controller refreshes the memory cells by supplying power to the memory by using the power switching means in the first operating mode, and stops the power supply to at least one circuit block by using the power supply switching means in the second operating mode so as to set up an operating mode in which transition between the first and second modes are repeated plural times. The power needed while such a semiconductor integrated circuit device including a memory element having a long refresh cycle is in a waiting mode is lowered, thereby reducing the overall power of the semiconductor integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括存储器，其包括存储器单元和电路块，电源开关装置和刷新控制器，并且具有第一和第二操作模式，其中，所述刷新控制器通过使用所述存储器单元向存储器供电来刷新存储器单元功率切换装置，并且在第二操作模式中通过使用电源切换装置来停止对至少一个电路块的电源，以便建立其中第一和第二模式之间的转换是重复多次。包括具有较长刷新周期的存储元件的这种半导体集成电路器件处于等待模式所需的功率降低，从而降低半导体集成电路器件的整体功率。

52. 发明申请

WO00003397A1 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：WO00003397A1
公开(公告)日：2000-01-20
申请号：PCT/JP1999/003747
申请日：1999-07-12
IPC分类号： G11C11/401 , G11C11/4093 , G11C11/407
CPC分类号： G11C11/4093
摘要： An integrated circuit comprises DRAMs and logics integrated in a single chip to reduce current consumption and peak current required for data transfer. When data are transferred from a DRAM array (1) to a logic section (3), the DRAM array (1), having large parasitic capacitance and heavy load, amplifies minute signal data read from a memory cell (5) to a low signal level at which a register (9) of the logic section (3) can amplify. A transfer gate (2) delivers the signal from the DRAM array (1) to the register (9) in the logic section (3), and the register (9) amplifies the signal to the power supply level. Rewriting to the memory cell (5) is performed at any given timing after completion of a data transfer from the DRAM array (1) to the logic section.
摘要翻译：集成电路包括集成在单个芯片中的DRAM和逻辑，以减少数据传输所需的电流消耗和峰值电流。当数据从DRAM阵列（1）传送到逻辑部分（3）时，具有大寄生电容和大负载的DRAM阵列（1）将从存储器单元（5）读取的微小信号数据放大到低信号逻辑部分（3）的寄存器（9）可放大的电平。传输门（2）将来自DRAM阵列（1）的信号传送到逻辑部分（3）中的寄存器（9），寄存器（9）将信号放大到电源电平。在完成从DRAM阵列（1）到逻辑部分的数据传送完成之后的任何给定的时刻，重写到存储器单元（5）。

53. 发明申请

WO99067789A1 METHOD AND APPARATUS FOR CONTROLLING THE DATA RATE OF A CLOCKING CIRCUIT 审中-公开
标题翻译：用于控制时钟电路的数据速率的方法和装置
公开(公告)号：WO99067789A1
公开(公告)日：1999-12-29
申请号：PCT/US1999/014228
申请日：1999-06-23
IPC分类号： G11C11/407 , G06F1/08 , G06F1/12 , G06F12/00 , G06F13/42 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/109 , G06F1/08 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.
摘要翻译：数据速率控制电路，其可在第一数据速率和第二数据速率之间编程。数据速率控制电路由时钟电路和开关电路构成。时钟电路在第一输入线上接收第一时钟信号，并具有接收第二时钟信号或稳态电压的第二输入线。开关电路将第二时钟信号或稳态电压选择性地耦合到时钟电路。当时钟电路接收到第二时钟信号时，时钟电路以双倍数据速率进行时钟，并且当时钟电路接收稳态电压时，时钟电路以单个数据速率进行时钟。开关电路包括在第二时钟信号和稳态电压之间切换输出信号的开关。时钟电路可以是本领域技术人员已知的许多电路中的任何一种，包括移位寄存器或计数器锁存器。

54. 发明申请

WO99046687A1 DATA TRANSMITTER 审中-公开
标题翻译：数据传输器
公开(公告)号：WO99046687A1
公开(公告)日：1999-09-16
申请号：PCT/JP1998/001032
申请日：1998-03-12
IPC分类号： G11C7/10 , G11C7/22 , G06F13/42 , G11C11/407
CPC分类号： G11C7/1084 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22
摘要： When a load capacitance difference including a cable line length difference and a parasitic element exists between parallel data lines, the propagating time lag between data reaches a level hard to ignore. Therefore, when particularly high-speed data having a short period are transmitted, the set-up time and hold time for data fetching cannot be secured and data are not transmitted normally. Since a data transmitter is provided with a circuit to discriminate reception without delay which compares the phases of a part or all of the bits of received data in a receiver that receives parallel data and a timing adjusting mechanism which adjusts the phase among parallel bits at the data fetching point of the receiver based on the results of the discriminating circuit, each data bit can be made to simultaneously arrive at the receiver. Therefore, the set-up time and hold time can be secured even when differences exist in the cable line length and load capacitance.
摘要翻译：当在并行数据线之间存在包括电缆线长度差和寄生元件的负载电容差时，数据之间的传播时间延迟难以忽略。因此，当发送具有短周期的特别高速数据时，不能确保用于数据获取的建立时间和保持时间，并且数据不能正常发送。由于数据发送器具有无延迟地鉴别接收的电路的电路，其比较接收并行数据的接收机中的接收数据的一部分或全部位的相位和调整在该并行数据的并行位之间的相位的定时调整机构基于识别电路的结果的接收机的数据取出点，可以使每个数据位同时到达接收机。因此，即使电缆线长度和负载电容存在差异，也可以确保设置时间和保持时间。

55. 发明申请

WO1998036419A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998036419A1
公开(公告)日：1998-08-20
申请号：PCT/JP1997000410
申请日：1997-02-17
申请人： HITACHI, LTD. , AYUKAWA, Kazushige , WATANABE, Takao , NARITA, Susumu
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G06F12/0215 , G06F13/1631 , G11C7/1072 , G11C8/12 , G11C11/005
摘要： A memory macro (MM) is a combination of functional modules such as a main amplifier module (13), memory bank modules (11) of which each memory bank operates independently, a power source circuit (14), etc. The storage capacity of the memory macro (MM) can be easily changed from a large capacity to a small one by changing the number of the memory bank modules (11). A control circuit (BKCONTH) in the memory bank modules (11) of the memory macro (MM) has an additional address comparing function (COMP). Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro (MM). In addition, a module (17) having a function such as a memory access sequence control is provided and, when memory access is made, identification information (ID) is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.
摘要翻译：存储器宏（MM）是功能模块的组合，诸如主放大器模块（13），每个存储器组独立地存储的存储体模块（11），电源电路（14）等。存储容量通过改变存储体模块（11）的数量，可以容易地将存储器宏（MM）从大容量改变为小容量。存储器宏（MM）的存储器组模块（11）中的控制电路（BKCONTH）具有附加地址比较功能（COMP）。因此，可以高速访问同一页面，而不需要在存储器宏（MM）之外提供任何控制电路。此外，提供具有诸如存储器访问顺序控制的功能的模块（17），并且当进行存储器访问时，在输入/输出地址或数据时发出识别信息（ID）。因此，可以通过使用ID检查数据和地址之间的一致性并控制存储器访问顺序来实现高速存储器访问，从而可以改变地址输入顺序和数据输出顺序。

56. 发明申请

WO1998025271A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998025271A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003548
申请日：1996-12-04
申请人： HITACHI, LTD. , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , MIYAMOTO, Toshio , NISHIMURA, Asao
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G11C11/409 , G11C11/406
摘要： A semiconductor integrated circuit device for high-speed data transfer, wherein wait control is eliminated to allow a logic circuit to access a DRAM during the self-refreshing period of the DRAM. The integrated circuit comprises a chip that includes a microcomputer incorporated with a CPU, memories and peripheral circuits, and a flash memory; and another chip that includes DRAMs and a logic circuit, such as an ASIC. The control of the DRAM depends on whether the DRAM is in the normal access period or in the self-refreshing period. In the DRAM self-refreshing period, the refreshing operations are canceled so that the logic circuit can access the DRAM when the logic circuit requests the access to the DRAM by using readout/write signals R/W.
摘要翻译：一种用于高速数据传输的半导体集成电路装置，其中消除了等待控制，以允许逻辑电路在DRAM的自刷新周期期间存取DRAM。集成电路包括芯片，其包括与CPU结合的微计算机，存储器和外围电路以及闪速存储器; 以及包括DRAM和诸如ASIC的逻辑电路的另一芯片。 DRAM的控制取决于DRAM是处于正常访问周期还是在自刷新期间。在DRAM自刷新周期中，刷新操作被取消，使得当逻辑电路通过使用读出/写入信号R / W请求访问DRAM时逻辑电路可以访问DRAM。

57. 发明申请

WO9802886A3 MEMORY WITH FAST DECODING 审中-公开
标题翻译：内存快速解码
公开(公告)号：WO9802886A3
公开(公告)日：1998-05-07
申请号：PCT/US9712648
申请日：1997-07-17
申请人： CHANG EDWARD C M , CHANG DEIRDRE S , CHANG DEREK S
发明人： CHANG EDWARD C M , CHANG DEIRDRE S , CHANG DEREK S
IPC分类号： G11C11/413 , G11C7/10 , G11C8/00 , G11C8/10 , G11C11/407
CPC分类号： G11C7/1042 , G11C7/1018 , G11C8/00 , G11C8/10
摘要： A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (501-50M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (401 and 402) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.
摘要翻译：公开了用于组织电子存储器以增加有效解码速度同时能够随机地寻址存储器中的存储位置的一组技术。存储器通常包含存储器阵列（41或51）和地址电路（40或50）。在一种存储器组织技术中，地址电路包含一组串联排列的解码段（501-50M）。每个解码段都部分解码输入存储器地址。在另一种存储器组织技术中，地址电路包含并行排列的多个解码段（401和402），每个解码段顺序解码输入存储器地址中的不同输入存储器地址，而不是每个其他解码段。并行存储器组织技术的变体可以与现成的存储器一起使用。

58. 发明申请

WO1997023877A1 IMPROVED SEMICONDUCTOR MEMORY WITH ROW DECODER OUTPUTTING ROW SELECTING SIGNAL AND ITS CONTROLLING METHOD 审中-公开
标题翻译：改进的半导体存储器与解码器输出选择信号及其控制方法
公开(公告)号：WO1997023877A1
公开(公告)日：1997-07-03
申请号：PCT/JP1995002658
申请日：1995-12-25
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , TAKAHASHI, Shinya , HONDA, Takashi
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G11C11/407
CPC分类号： G11C11/4096 , G11C11/4087
摘要： A semiconductor memory (100) in which the driving potential given to an inverter (125) constituting the output part of a row decoder (103) which outputs a row selecting signal to a column line (CL) is lower than the power supply potential Vcc given from the outside. The timing at which a bit line is connected to the data bus is determined by the degree of amplification of the potential of the bit line, realizing a semiconductor memory which operates at high speeds reliably.
摘要翻译：一种半导体存储器（100），其中构成向列线（CL）输出行选择信号的行解码器（103）的输出部分的反相器（125）的驱动电位低于电源电位Vcc 从外面给予位线连接到数据总线的定时由位线的电位的放大程度确定，实现了可靠地高速运行的半导体存储器。

59. 发明申请

WO1997008704A1 CIRCUITS, SYSTEMS AND METHODS FOR CONTROLLING SUBSTRATE BIAS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：用于控制集成电路中基板偏移的电路，系统和方法
公开(公告)号：WO1997008704A1
公开(公告)日：1997-03-06
申请号：PCT/US1996013869
申请日：1996-08-29
申请人： CIRRUS LOGIC, INC.
发明人： CIRRUS LOGIC, INC. , RUNAS, Michael, E.
IPC分类号： G11C11/407
CPC分类号： G11C5/025 , G11C5/146 , G11C11/4074
摘要： Substrate bias control circuitry (100) is provided which includes a bias sensor (101) for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator (102) is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor (101). A first charge pump (103) is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump (105) is provided for pumping electrons into the substrate in response to the second driving signal.
摘要翻译：提供了衬底偏置控制电路（100），其包括用于测量衬底的偏置电压并产生控制信号和响应的偏置传感器（101）。提供主振荡器（102），用于产生第一驱动信号，通过由偏置传感器（101）产生的控制信号调节的第一驱动信号的频率。第一电荷泵（103）被提供用于响应于第一驱动信号将电子泵送到衬底中。从振荡器产生第二驱动信号，使用锁相环从第一驱动信号的频率确定第二驱动信号的频率。提供第二电荷泵（105），用于响应于第二驱动信号将电子泵送到衬底中。

60. 发明申请

WO1989012303A1 MEMORY DEVICE 审中-公开
标题翻译：内存设备
公开(公告)号：WO1989012303A1
公开(公告)日：1989-12-14
申请号：PCT/GB1989000651
申请日：1989-06-12
申请人： CAMBRIDGE COMPUTER LIMITED , SINCLAIR, Clive, Miles , WESTWOOD, James , WRIGHT, David
发明人： CAMBRIDGE COMPUTER LIMITED
IPC分类号： G11C11/407
CPC分类号： G11C11/4074 , G11C11/406
摘要： A dynamic RAM memory device with DRAM (10) comprises a control unit (22) detecting when memory accesses are required for read, write or refresh. This unit (22) controls a voltage control circuit (26) which provides operating voltage (e.g. +5v) to the DRAM (10) but switches the voltage to a low level (e.g. 0.5v) in intervals between accesses. The low level is such that the current taken by the DRAM (10) is substantially zero.
摘要翻译：具有DRAM（10）的动态RAM存储器件包括控制单元（22），用于检测存储器访问是否需要读取，写入或刷新。该单元（22）控制向DRAM（10）提供工作电压（例如+ 5v）的电压控制电路（26），但是在访问之间的间隔中将电压切换到低电平（例如0.5v）。低电平使得DRAM（10）占据的电流基本为零。

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