专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO2021059582A1 半導体装置审中-公开
公开(公告)号：WO2021059582A1
公开(公告)日：2021-04-01
申请号：PCT/JP2020/019309
申请日：2020-05-14
申请人：ヌヴォトンテクノロジージャパン株式会社
发明人：中西　和幸
IPC分类号： H03K3/037 , H03K3/356 , H01L21/8238 , H01L27/092 , H03K19/003
摘要：半導体装置は、第１の反転回路（ｉ１）、第２の反転回路（ｉ２）、第３の反転回路（ｉ３）および第４の反転回路（ｉ４）から成る第１のラッチ回路（Ｌ１）と、第１型ウェル領域（Ｗｐ１、Ｗｐ２）と、第２型ウェル領域（Ｗｎ１）とを備え、平面視において、ドレイン（ｐ１）とドレイン（ｐ３）との距離よりも、ドレイン（ｐ１）とドレイン（ｐ４）との距離の方が小さい。

52. 发明申请

WO2019229593A1 半導体装置审中-公开
公开(公告)号：WO2019229593A1
公开(公告)日：2019-12-05
申请号：PCT/IB2019/054254
申请日：2019-05-23
申请人：株式会社半導体エネルギー研究所
发明人：小林英智 , 池田隆之 , 中川貴史 , 廣瀬丈也 , 勝井秀一
IPC分类号： H01L29/786 , H01L21/822 , H01L21/8234 , H01L21/8242 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/108 , H03K3/356
摘要：しきい値電圧の補正によって、演算の精度を高めた半導体装置を提供する。第１、第２電流源回路を有する半導体装置であって、第２電流源回路は、第１電流源回路と同一の構成を有する。第１電流源回路は、第１、第２トランジスタと、第１容量素子と、第１乃至第３ノードと、を有する。第１トランジスタの第１端子は、第１ノードに電気的に接続され、第１トランジスタのバックゲートは、第２トランジスタの第１端子と、第１容量素子の第１端子と、に電気的に接続されている。第１トランジスタのゲートは、第２ノードに電気的に接続され、第１容量素子の第２端子は、第１トランジスタの第２端子に電気的に接続されている。第１電流源回路の第１ノードは、第１、第２電流源回路のそれぞれの第２ノードに電気的に接続されている。第１トランジスタのバックゲートに補正電圧を書き込むことで、第１トランジスタのしきい値電圧の補正を行う。

53. 发明申请

WO2019190810A1 SUPERCONDUCTING INTEGRATED CIRCUITS WITH CLOCK SIGNALS DISTRIBUTED VIA INDUCTIVE COUPLING 审中-公开
公开(公告)号：WO2019190810A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/022834
申请日：2019-03-19
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： LUO, Henry Y.
IPC分类号： H03K3/356 , H03K3/38
摘要： Superconducting integrated circuits with clock signals distributed via an inductive coupling and related methods are provided. A method includes providing a D flip-flop having a clock terminal coupled to receive clock pulses from a clock line, a data input terminal, and a data output terminal. The D flip-flop may further include a first Josephson junction (JJ) coupled between a first terminal and a second terminal. The D flip-flop may further include a superconducting quantum interference device (SQUID) coupled between a third terminal and a fourth terminal, where an inductive loop, formed between the first JJ and the SQUID, is configured to in response to receiving a first clock pulse, store a fluxon when a state of the input data signal is high, and is configured to in response to receiving a second clock pulse to annihilate the stored fluxon when a state of the input data signal is low.

54. 发明申请

WO2019143302A1 CIRCUIT, METHOD FOR SIZING AN ASPECT RATIO OF TRANSISTORS OF A CIRCUIT, AND CIRCUIT ARRANGEMENT 审中-公开
公开(公告)号：WO2019143302A1
公开(公告)日：2019-07-25
申请号：PCT/SG2019/050036
申请日：2019-01-22
申请人： NANYANG TECHNOLOGICAL UNIVERSITY
发明人： CHANG, Joseph Sylvester , CHONG, Kwen Siong , LWIN, Ne Kyaw Zwa , HARIHARAKRISHNAN, Sivaramakrishnan
IPC分类号： H03K19/003 , H03K3/356
摘要： According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

55. 发明申请

WO2018222344A2 APPARATUS AND METHOD FOR CALIBRATING A RECEIVER WITH A DECISION FEEDBACK EQUALIZER (DFE) 审中-公开
公开(公告)号：WO2018222344A2
公开(公告)日：2018-12-06
申请号：PCT/US2018/031341
申请日：2018-05-07
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Minha
IPC分类号： H04L7/00 , H03K3/356 , H04L25/03
CPC分类号： H04L25/03267 , H03K3/356139 , H04L1/0071 , H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch to output a target signal sample; a E sample digital to analog converter coupled to the E sample latch to input a target voltage to the E sample latch; a sample latch to output a signal sample; and a voltage digital to analog converter coupled to the E sample latch and the sample latch to generate a bias voltage, wherein the bias voltage is inputted to the E sample latch and the sample latch. The DFE input section may further include a latch offset decoder to scale the bias voltage and a summing amplifier to receive an analog input waveform to the DFE input section.

56. 发明申请

WO2018182961A1 HIGH-SPEED LEVEL SHIFTER 审中-公开
公开(公告)号：WO2018182961A1
公开(公告)日：2018-10-04
申请号：PCT/US2018/022018
申请日：2018-03-12
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , CHEN, Po-Hung , AHMED, Fahad , JUNG, Changho , YOON, Sei Seung , LI, David
IPC分类号： H03K3/356 , G11C5/14 , G11C7/12 , G11C8/10 , H03K19/0185
摘要： A circuit (200) including an output node (OUT) and a cross-coupled pair of semiconductor devices (204, 214) configured to provide, at the output node, an output signal in a second voltage domain (VDDH) based on an input signal in a first voltage domain (VDDL) is described herein. The circuit further includes a pull-up assist circuit (230) coupled to the output node; and a look-ahead circuit (220) coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

57. 发明申请

WO2018005086A1 HIGH SPEED VOLTAGE LEVEL SHIFTER 审中-公开
标题翻译：高速电压电平转换器
公开(公告)号：WO2018005086A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037338
申请日：2017-06-13
申请人： QUALCOMM INCORPORATED
发明人： NARAYANAN, Venkat , VATTIKONDA, Rakesh , LU, De , VILANGUDIPITCHAI, Ramaprasath , SINHAROY, Samrat , CHEN, Rui
IPC分类号： H03K3/356 , H03K19/0185 , H03K19/096
CPC分类号： H03K19/018521 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/01855 , H03K19/0963
摘要： In one embodiment, a voltage level shifter (810) includes a first p-type metal-oxide-semiconductor transistor (835) having a gate configured to receive an input signal (D) in a first power domain, and a second PMOS transistor (840), wherein the first and second PMOS transistors are coupled in series between a supply voltage (vddout) of a second power domain and a node (820). The voltage level shifter also includes an inverter (850) having an input coupled to the node and an output (Z) coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor transistor (830) having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.
摘要翻译：在一个实施例中，电压电平移位器（810）包括第一p型金属氧化物半导体晶体管（835），其具有被配置为接收第一功率域和第二PMOS晶体管（840），其中第一和第二PMOS晶体管串联耦合在第二电源域的电源电压（vddout）和节点（820）之间。电压电平移位器还包括反相器（850）和第一n型金属氧化物半导体晶体管（830），第一n型金属氧化物半导体晶体管（830）具有耦合到节点的输入和耦合到第二PMOS晶体管的栅极的输出（Z）栅极，被配置为在第一电源域中接收输入信号，其中第一NMOS晶体管耦合在节点和地之间。

58. 发明申请

WO2018005085A1 HIGH SPEED VOLTAGE LEVEL SHIFTER 审中-公开
标题翻译：高速电压电平转换器
公开(公告)号：WO2018005085A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037335
申请日：2017-06-13
申请人： QUALCOMM INCORPORATED
发明人： NARAYANAN, Venkat , VATTIKONDA, Rakesh , LU, De , VILANGUDIPITCHAI, Ramaprasath , SINHAROY, Samrat , CHEN, Rui
IPC分类号： H03K3/012 , H03K3/356
摘要： A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second power domain, a third input (257), and an output (Z). The voltage level shifter also includes a second NOR gate (220) having a first input (222) configured to receive a second input signal (D) in the first power domain, a second input (225) configured to receive the enable signal in the second power domain, a third input (227) coupled to the output of the first NOR gate, and an output (Z_N) coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.
摘要翻译：电压电平移位器包括具有被配置为在第一电力域中接收第一输入信号（D_N）的第一输入端（252）的第一或非门（250），被配置为在第一输入端以在第二电力域，第三输入（257）和输出（Z）中接收使能信号（ENB）。所述电压电平移位器还包括第二NOR门（220），所述第二NOR门具有被配置为在所述第一电力域中接收第二输入信号（D）的第一输入（222），被配置为在所述第一电力域中接收所述使能信号第二电源域，耦合到第一或非门的输出的第三输入（227）以及耦合到第一或非门的第三输入的输出（Z_N）。第一和第二NOR门由第二电源域的电源供电。

59. 发明申请

WO2017172329A1 POWER EFFICIENT VOLTAGE LEVEL TRANSLATOR CIRCUIT 审中-公开
标题翻译：功率高效的电压电平翻译器电路
公开(公告)号：WO2017172329A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/021935
申请日：2017-03-10
申请人： QUALCOMM INCORPORATED
发明人： NADKARNI, Rahul Krishnakumar , CORREALE JR, Anthony
IPC分类号： H03K3/012 , H03K3/356 , H03K19/00 , H03K19/017
摘要： Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage (vdd1) of the first voltage domain and a second supply voltage (vdd2) of the second voltage domain are different, the voltage level translator (250) translates an input signal (a, a_n) in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit (252) is configured to bypass the voltage level translator (250) and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit (275) is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.
摘要翻译：所公开的系统和方法涉及功率高效的电压电平转换器。在其中第一电压域的第一电源电压（vdd1）和第二电压域的第二电源电压（vdd2）不同的正常模式中，电压电平转换器（250）将输入信号（a，a_n）转换为第一电压域到第二电压域中的输出信号。在其中第一电源电压和第二电源电压基本相同的旁路模式中，旁路电路（252）被配置为旁路电压电平转换器（250）并且提供输入信号作为第一电压域中的输出信号，从而避免旁路模式中的电压电平转换器引起的延迟。此外，断电电路（275）被配置为在旁路模式下使电压电平转换器掉电，但不在正常模式下。

60. 发明申请

WO2017144855A1 CORRELATED ELECTRON MEMORY ELEMENT-BASED LATCHING CIRCUITS 审中-公开
标题翻译：相关的基于电子存储元件的闩锁电路
公开(公告)号：WO2017144855A1
公开(公告)日：2017-08-31
申请号：PCT/GB2017/050336
申请日：2017-02-09
申请人： ARM LTD
发明人： AITKEN, Robert Campbell , CHANDRA, Vikas , SANDHU, Bal S , LATTIMORE, George McNeil , DAS, Shidhartha , BIGGS, John Philip , SAVANTH, Parameshwarappa Anand Kumar , MYERS, James Edward
IPC分类号： G11C13/00 , G11C14/00 , H01L49/00 , H03K3/356
CPC分类号： G11C14/009 , G11C13/0007 , G11C13/004 , G11C13/0069 , H03K3/356008
摘要： According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron switch, hereinafter termed CES, element. The latching circuitry further comprises a control circuit coupled to the at least one CES element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
摘要翻译：根据本公开的一个实施例，一种装置包括锁存电路，其中锁存电路包括至少一个相关电子开关，以下称为CES元件。锁存电路还包括耦合到至少一个CES元件的控制电路。控制电路被配置为接收至少一个控制信号。基于至少一个控制信号，执行将数据存储到锁存电路和从锁存电路输出数据中的至少一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式